ST5451 Ver la hoja de datos (PDF) - STMicroelectronics
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ST5451 Datasheet PDF : 34 Pages
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ST5451
DEMULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 0)
NAME
A0/A5
D0/D7
R/W
E
PIN
3-8
17-24
27
26
TYPE
I
I/O
I
I
FUNCTION
Address Bus. To transfer addresses from µP to ST5451.
Data Bus. To transfer data between µP and ST5451.
Read/Write. ”1” indicates a read operation; ”0” a write operation.
Enable. Read/write operations are synchronized with this signal; its
falling edge marks the end of an operation.
MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 1 I/M = 1)
NAME
AD0/AD7
WR
RD
ALE
PIN
17-24
27
26
3
TYPE
I/O
I
I
I
FUNCTION
Address Data Bus. To transfer addresses and data between µP
and ST5451.
Write. This signal indicates a write operation.
Read. This signal indicates a read operation.
Falling edge latches the address from the external A/D Bus.
MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 1; I/M = 0)
NAME
AD0/AD7
R/W
DS
AS
PIN
17-24
27
26
3
TYPE
I/O
I
I
I
FUNCTION
Address Data Bus. To transfer addresses and data between µP
and ST5451.
Read/Write. ”1” Indicates a write operation; ”0” a write operation.
Data Strobe. Read/Write operations are synchronized with this
signal: its falling edge marks the end of an operation.
Address Strobe. Falling edge latches the address from the external
A/D Bus.
DMA (direct memory access): only when MULT = 1
NAME
PIN
DMA REQ X
7
DMA REQ R
5
DMA ACK X
8
DMA ACK R
6
TYPE
O
O
I
I
FUNCTION
Direct Memory Access Requests: these outputs are asserted by
the device to request an exchange of byte from the memory.
Direct Memory Access Acknowledge: these inputs are asserted by
the DMA controller to signal to the HDLC controller that a byte is
being transferred in response to a previous transfer request.
GCI INTERFACE
NAME
PIN
DOUT
15
DIN
12
CLK
11
FS
13
DEN
10
TYPE
I/O
I/O
I
I
I
FUNCTION
Data output for B and D channels. In GCI mode it outputs B1,
B2, M and C/I channels. In TE mode (GCI-SCIT) it can invert to
input data for M’ and C/I’ channels (See Table 2).
Data input for B and D channels. In GCI mode it inputs B1, B2, M
and C/I channels. In TE mode (GCI-SCIT) it can invert to output
data for M’ and C/I’ channels (See Table 2).
Data Clock. It determines the data shift rate for GCI channels on
the module interface.
Frame synchronization. This signal is a 8 kHz signal for frame
synchronization. The front edge gives the time reference of the first
bit in the frame.
Data Enable. In TE mode, this pin is a normally low input pulsing
high to indicate the active bit times for D channel transmit at DOUT
pin. It is intended to be gated with CLK to control the shifting of
data from HDLC controller to S interface device.
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