ST5451 Ver la hoja de datos (PDF) - STMicroelectronics
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ST5451 Datasheet PDF : 34 Pages
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ST5451
TABLE 3
N (number of bytes in the
frame received without CRC)
N
1 Min
2
3
30
31
32
33
62
63
64
222
223
224
256
257
-
Counter
765
4321 0
n
m
000
00001
000
00010
000
00011
000
11110
000
11111
001
00000
001
00001
001
11110
001
11111
010
00000
110
11110
110
11111
111
11111
111
00000
111
00001
111
-
n (number of 32 bytes blocks
received )
n
0
0
0
0
0
1
1
1
1
2
6
6
7
7
7
7
MONR2
Monitor Receive Register 2
After reset FFH
(GCI and TE mode only)
The value read from MONR2 gives the
value of the byte received from M
channel in 2nd GCI channel.
TSR
Time Slot Register
After reset 00
TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
In GCI mode (MDS1= 1 in CF Register)
a) CCS=1 in CF Reg. (64 Kbit/s)
Then: TSR2 indicates B1 or B2
TSR4/7 indicate position of
GCI channel
b) CCS=0 in CF Reg. (16 Kbit/s)
Then: TSR4/7 indicate position of
GCI and its D channel
In Multiplexed Mode
(MDS1=0 in CF Register)
a) CCS=1 in CF Reg. (64 Kbit/s)
Then: TSR2/7 indicate channel
position in the 64 time slots
multiplex
b) CCS=0 in CF Reg. (16 Kbit/s)
Then: TSR0/7 indicate channel
position in the 256 time slots
multiplex.
10/34
CA
Configurationn Register A
After reset 00
CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
SAPI 0 is recognized
SAPI 63
SAPI x
SAPI y
TEI 127
TEI z
TEI t
Address filter active
CA0 = 1
CA1 = 1
CA2 = 1
CA3 = 1
CA4 = 1
CA5 = 1
CA6 = 1
CA7 = 1
CB
Configuration register B
After reset 00
Content of CB indicate SAPI x value
High Order 6 Bits
SAPI
0
0
CC
Configuration Register C
After reset 00
Content of CC indicate SAPI y value
High Order 6 Bits
SAPI
0
0
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