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SST36VF1601E Datasheet PDF : 35 Pages
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16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Sector-Erase/Block-Erase Operation
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis. The
sector architecture is based on a uniform sector size of 2
KWord. The Block-Erase mode is based on a uniform block
size of 32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with a Sector-
Erase command (30H) and sector address (SA) in the last
bus cycle. The Block-Erase operation is initiated by execut-
ing a six-byte command sequence with Block-Erase com-
mand (50H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The inter-
nal Erase operation begins after the sixth WE# pulse. Any
commands issued during the Sector- or Block-Erase opera-
tion are ignored except Erase-Suspend and Erase-
Resume. See Figures 13 and 14 for timing waveforms.
Chip-Erase Operation
The devices provide a Chip-Erase operation, which allows
the user to erase all sectors/blocks to the “1” state. This is
useful when a device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. Any com-
mands issued during the Chip-Erase operation are
ignored. See Table 5 for the command sequence, Figure
12 for timing diagram, and Figure 27 for the flowchart.
When WP# is low, any attempt to Chip-Erase will be
ignored.
Data Sheet
Erase-Suspend/Erase-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode no more than 10 µs
after the Erase-Suspend command had been issued. (TES
maximum latency equals 10 µs.) Valid data can be read
from any sector or block that is not suspended from an
Erase operation. Reading at address location within erase-
suspended sectors/blocks will output DQ2 toggling and
DQ6 at “1”. While in Erase-Suspend mode, a Program
operation is allowed except for the sector or block selected
for Erase-Suspend. To resume Sector-Erase or Block-
Erase operation which has been suspended, the system
must issue an Erase-Resume command. The operation is
executed by issuing a one-byte command sequence with
Erase Resume command (30H) at any address in the one-
byte sequence.
Write Operation Status Detection
These devices provide one hardware and two software
means to detect the completion of a Write (Program or
Erase) cycle in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two sta-
tus bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The
End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ7), or Toggle Bit (DQ6) Read may
be simultaneous with the completion of the Write cycle. If
this occurs, the system may get an erroneous result, i.e.,
valid data may appear to conflict with either DQ7 or DQ6. In
order to prevent spurious rejection if an erroneous result
occurs, the software routine should include a loop to read
the accessed location an additional two (2) times. If both
Reads are valid, then the Write cycle has completed, other-
wise the rejection is valid.
©2005 Silicon Storage Technology, Inc.
3
S71274-03-000
11/05
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