SST25PF020B(2012) Ver la hoja de datos (PDF) - Microchip Technology
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SST25PF020B Datasheet PDF : 33 Pages
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SST25PF020B
CE#
MODE 3 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
SCK MODE 0
SI
05
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
25135 RDSRseq.0
FIGURE 4-14:
READ-STATUS-REGISTER (RDSR) SEQUENCE
4.5.11 READ-STATUS-REGISTER (RDSR1)
The Read-Status-Register 1 (RDSR1) instruction
allows reading of the status register 1. CE# must be
driven low before the RDSR instruction is entered and
remain low until the status data is read. Read-Status-
Register 1 is continuous with ongoing clock cycles until
it is terminated by a low to high transition of the CE#.
See Figure 4-15 for the RDSR instruction sequence.
CE#
MODE 3 0
1
2
3
4
5
6
SCK MODE 0
SI
35
MSB
HIGH IMPEDANCE
SO
7
8
9 10 11 12 13 14
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
25135 RDSR1seq.0
FIGURE 4-15:
READ-STATUS-REGISTER 1 (RDSR1) SEQUENCE
4.5.12 WRITE-ENABLE (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to 1 allowing
Write operations to occur. The WREN instruction must
be executed prior to any Write (Program/Erase) opera-
tion. The WREN instruction may also be used to allow
execution of the Write-Status-Register (WRSR) instruc-
tion; however, the Write-Enable-Latch bit in the Status
Register will be cleared upon the rising edge CE# of the
WRSR instruction. CE# must be driven high before the
WREN instruction is executed.
CE#
MODE 3
SCK MODE 0
0 1 23456 7
FIGURE 4-16:
SI
06
MSB
SO
HIGH IMPEDANCE
25135 WREN.0
WRITE ENABLE (WREN) SEQUENCE
2012 Microchip Technology Inc.
DS25135A-page 15
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