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SST25VF016B

16 Mbit SPI Serial Flash

Silicon Storage Technology 

Data Sheet

Write-Status-Register (WRSR)

The Write-Status-Register instruction writes new values to

the BP3, BP2, BP1, BP0, and BPL bits of the status regis-

ter. CE# must be driven low before the command

sequence of the WRSR instruction is entered and driven

high before the WRSR instruction is executed. See Figure

19 for EWSR or WREN and WRSR instruction sequences.

Executing the Write-Status-Register instruction will be

ignored when WP# is low and BPL bit is set to “1”. When

the WP# is low, the BPL bit can only be set from “0” to “1” to

lock-down the status register, but cannot be reset from “1”

to “0”. When WP# is high, the lock-down function of the

16 Mbit SPI Serial Flash

SST25VF016B

BPL bit is disabled and the BPL, BP0, and BP1 and BP2

bits in the status register can all be changed. As long as

BPL bit is set to 0 or WP# pin is driven high (VIH) prior to the

low-to-high transition of the CE# pin at the end of the

WRSR instruction, the bits in the status register can all be

altered by the WRSR instruction. In this case, a single

WRSR instruction can set the BPL bit to “1” to lock down

the status register as well as altering the BP0, BP1, and

BP2 bits at the same time. See Table 2 for a summary

description of WP# and BPL functions.

CE#

MODE 3

SCK MODE 0

0 1 2345 6 7

MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

MODE 0

SI

50 or 06

MSB

01

MSB

STATUS

REGISTER IN

76543210

MSB

SO

HIGH IMPEDANCE

FIGURE 19: Enable-Write-Status-Register (EWSR) or

Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence

1271 EWSR.0

©2008 Silicon Storage Technology, Inc.

18

S71271-03-000

9/08

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