IDT723612L20PQFG Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT723612L20PQFG Datasheet PDF : 25 Pages
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IDT723612
CMOS SYNCBiFIFOTM 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
RESET
The IDT723612 is reset by taking the Reset (RST) input LOW for at least
four port-A clock (CLKA) and four port-B Clock (CLKB) LOW-to-HIGH
transitions. The Reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of each FIFO and forces
the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW, the Almost-
Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA, AFB) HIGH. A
reset also forces the Mailbox Flags (MBF1, MBF2) HIGH. After a reset, FFA
is set HIGH after two LOW-to-HIGH transitions of CLKA and FFB is set HIGH
after two LOW-to-HIGH transitions of CLKB. The device must be reset after
power up before data is written to its memory.
TABLE 1 — FLAG PROGRAMMING
FS1
FS0 RST
H
H
↑
H
L
↑
L
H
↑
L
L
↑
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
16
12
8
4
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Empty registers (X) with the values selected by the Flag Select (FS0,
FS1) inputs. The values that can be loaded into the registers are shown in
Table 1.
FIFO WRITE/READ OPERATION
The state of port-A data A0-A35 outputs is controlled by the port-A Chip
Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs
are in the high-impedance state when either CSA or W/RA is HIGH. The A0-
A35 outputs are active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA
is LOW, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by
a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA is HIGH (see Table 2).
The port-B control signals are identical to those of port A. The state of the
port-B data (B0-B35) outputs is controlled by the port-B Chip Select (CSB) and
the port-B Write/Read select (W/RB). The B0-B35 outputs are in the high-
impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are
active when both CSB and W/RB are LOW.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is
LOW, and FFB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by
a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is
HIGH, MBB is LOW, and EFB is HIGH (see Table 3).
TABLE 2 — PORT-A ENABLE FUNCTION TABLE
CSA W/RA ENA
H
X
X
L
H
L
L
H
H
L
H
H
L
L
L
L
L
H
L
L
L
L
L
H
MBA CLKA
X
X
X
X
L
↑
H
↑
L
X
L
↑
H
X
H
↑
A0-A35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO2 Output Register
Active, FIFO2 Output Register
Active, Mail2 Register
Active, Mail2 Register
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
CSB
W/RB ENB
MBB CLKB
B0-B35 Outputs
H
X
X
X
X
In High-Impedance State
L
H
L
X
X
In High-Impedance State
L
H
H
L
↑
In High-Impedance State
L
H
H
H
↑
In High-Impedance State
L
L
L
L
X
Active, FIFO1 Output Register
L
L
H
L
↑
Active, FIFO1 Output Register
L
L
L
H
X
Active, Mail1 Register
L
L
H
H
↑
Active, Mail1 Register
10
Port Functions
None
None
CFOIFMOM1 EWRriCteIAL AND INDUSTRIAL
Mail1 Write
None
FIFO2 Read
None
Mail2 Read (Set MBF2 HIGH)
Port Functions
None
None
FIFO2 Write
Mail2 Write
None
FIFO1 read
None
Mail1 Read (Set MBF1 HIGH)
FEBRUARY 13, 2009
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