IDT723612L20PQF(1997) Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT723612L20PQF
(Rev.:1997)

BiCMOS SyncBiFIFO 64 x 36 x 2

Integrated Device Technology 

IDT723612 BiCMOS SyncBiFIFO™

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONTINUED)

SYMBOL NAME

I/O

DESCRIPTION

MBB

MBF1

MBF2

ODD/

EVEN

PEFA

PEFB

PGA

PGB

RST

W/RA

W/RB

Port-B Mailbox

Select

Mail1 Register Flag

Mail2 Register Flag

Odd/Even Parity

Select

Port-A Parity Error

Flag

Port-B Parity Error

Flag

Port-A Parity

Port-B Parity

Generation

Reset

Port-A Write/Read

Select

Port-B Write/Read

Select

I A HIGH level on MBB chooses a mailbox register for a port-B read or write

operation. When the B0-B35 outputs are active, a HIGH level on MBB selects

data from the mail1 register for output, and a LOW level selects FIFO1

output register data for output.

O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to

the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set

LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-

B read is selected and MBB is HIGH. MBF1 is set HIGH when the device is

reset.

O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to

the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set

LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-

A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is

reset.

I Odd parity is checked on each port when ODD/EVEN is HIGH, and even

parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the

type of parity generated for each port if parity generation is enabled for a read

operation.

O When any byte applied to terminals A0-A35 fails parity, PEFA is LOW.

(Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the

most significant bit of each byte serving as the parity bit. The type of parity

checked is determined by the state of the ODD/EVEN input. The parity trees

used to check the A0-A35 inputs are shared by the mail2 register to generate

parity if parity generation is selected by PGA. Therefore, if a mail2 read with

parity generation is setup by having W/RA LOW, MBA HIGH, and PGA HIGH,

the PEFA flag is forcedHIGH regardless of the A0-A35 inputs.

O When any byte applied to terminals B0-B35 fails parity, PEFB is LOW.

(Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most

significant bit of each byte serving as the parity bit. The type of parity

checked is determined by the state of the ODD/EVEN input. The parity trees

used to check the B0-B35 inputs are shared by the mail1 register to generate

parity if parity generation is selected by PGB. Therefore, if a mail1 read with

parity generation is setup by having W/RB LOW, MBB HIGH, and PGB HIGH,

the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs.

I Parity is generated for data reads from port A when PGA is HIGH. Genera-

tion The type of parity generated is selected by the state of the ODD/EVEN

input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The

generated parity bits are output in the most significant bit of each byte.

I Parity is generated for data reads from port B when PGB s HIGH. The type of

parity generated is selected by the state of the ODD/EVEN input. Bytes are

organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity

bits are output in the most significant bit of each byte.

I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-

HIGH transitions of CLKB must occur while RST is LOW. This sets the AFA,

AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA, AEB, FFA, and

FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the

FS1 and FS0 inouts to select almost-full and almost-empty flag offset.

I A HIGH selects a write operation and a LOW selects a read operation on

port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the

high-impedance state when W/RA is HIGH.

I A HIGH selects a write operation and a LOW selects a read operation on

port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the

high-impedance state when W/RB is HIGH.

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