IDT723612L20PF(1997) Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT723612L20PF Datasheet PDF : 29 Pages
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IDT723612 BiCMOS SyncBiFIFO™
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTIONS
RESET
The IDT723612 is reset by taking the reset (RST) input
LOW for at least four port-A clock (CLKA) and four port-B clock
(CLKB) LOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of each FIFO and forces the
full flags (FFA, FFB) LOW, the empty flags (EFA, EFB) LOW,
the almost-empty flags (AEA, AEB) LOW and the almost-full
flags (AFA, AFB) HIGH. A reset also forces the mailbox flags
(MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two
LOW-to-HIGH transitions of CLKA and FFB is set HIGH after
two LOW-to-HIGH transitions of CLKB. The device must be
reset after power up before data is written to its memory.
ALMOST-FULL AND
FS1 FS0 RST ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H
H
↑
16
H
L
↑
12
L
H
↑
8
L
L
↑
4
Table 1. Flag Programming
A LOW-to-HIGH transition on the RST input loads the
almost-full and almost-empty registers (X) with the values
selected by the flag-select (FS0, FS1) inputs. The values that
can be loaded into the registers are shown in Table 1.
FIFO WRITE/READ OPERATION
The state of port-A data A0-A35 outputs is controlled by
the port-A chip select (CSA) and the port-A write/read select
(W/RA). The A0-A35 outputs are in the high-impedance state
when either CSA or W/RA is HIGH. The A0-A35 outputs are
active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH. Data is
read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA is HIGH (see Table 2).
The port-B control signals are identical to those of port A.
The state of the port-B data (B0-B35) outputs is controlled by
the port-B chip select (CSB) and the port-B write/read select
(W/RB). The B0-B35 outputs are in the high-impedance state
when either CSB or W/RB is HIGH. The B0-B35 outputs are
active when both CSB and W/RB are LOW.
Data is loaded into FIFO2 from the B0-B35 inputs on a
LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is
HIGH, ENB is HIGH, MBB is LOW, and FFB is HIGH. Data is
read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH
CSA
H
L
L
L
L
L
L
L
W/RA
X
H
H
H
L
L
L
L
ENA
X
L
H
H
L
H
L
H
MBA
X
X
L
H
L
L
H
H
CLKA
X
X
↑
↑
X
↑
X
↑
A0-A35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO2 Output Register
Active, FIFO2 Output Register
Active, Mail2 Register
Active, Mail2 Register
Table 2. Port-A Enable Function Table
Port Functions
None
None
FIFO1 Write
Mail1 Write
None
FIFO2 Read
None
Mail2 Read (Set MBF2 HIGH)
CSB
H
L
L
L
L
L
L
L
W/RB
X
H
H
H
L
L
L
L
ENB
X
L
H
H
L
H
L
H
MBB
X
X
L
H
L
L
H
H
CLKB
X
X
↑
↑
X
↑
X
↑
B0-B35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO1 Output Register
Active, FIFO1 Output Register
Active, Mail1 Register
Active, Mail1 Register
Table 3. Port-B Enable Function Table
Port Functions
None
None
FIFO2 Write
Mail2 Write
None
FIFO1 read
None
Mail1 Read (Set MBF1 HIGH)
9
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