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IDT71B74 Ver la hoja de datos (PDF) - Integrated Device Technology

Número de pieza
componentes Descripción
Fabricante
IDT71B74
IDT
Integrated Device Technology IDT
IDT71B74 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
MATCH TIMING(1)
COMMERCIAL TEMPERATURE RANGE
ADDRESS
t ADM
tCSM
t MHA
CS
tCSMHI (2)
OE
tOEMHI (2)
WE
tWEMHI (2)
RESET
DATA
VALID READ DATA
VALID MATCH
DATA
MATCH
t DAM
MATCH
t MHD
MATCH VALID
NO MATCH
NOTES:
1. It is not recommended to float data and address input pins while the MATCH pin is active.
2. Transition is measured at ±200mV from steady state.
t RSMHI (2)
3013 drw 13
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8 71B74S10 71B74S12 71B74S15
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max.
Reset Cycle
tRSPW(1) Reset Pulse Width
30 — 35 — 35 — 40 —
tWERS
WE HIGH to Reset HIGH
5—
5—
5
5
tRSRC
tPORS(2)
Reset HIGH to WE LOW
Power On Reset
25 — 25 — 25 — 30 —
100 — 100 — 100 — 120 —
NOTES:
1. Recommended duty cycle = 10% maximum.
2. This parameter is guaranteed with the AC Load (Figure 1) by device characterization, but is not production tested.
71B74S20
Min. Max. Unit
45 — ns
5
— ns
30 — ns
120 — ns
3013 tbl 13
RESET TIMING
RESET
WE
tRSPW
t WERS
tRSRC
3013 drw 14
14.1
8

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