SPT9691 Ver la hoja de datos (PDF) - Cadeka Microcircuits LLC.
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SPT9691 Datasheet PDF : 10 Pages
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TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the comparator is shown in
figure 3. Although it needs few external components and is
easy to apply, there are several conditions that should be
noted to achieve optimal performance. The very high operat-
ing speeds of the comparator require careful layout, decou-
pling of supplies, and proper design of transmission lines.
Since the SPT9691 comparator is a very high frequency and
high gain device, certain layout rules must be followed to
avoid oscillations. The comparator should be soldered to the
board with component lead lengths kept as short as possible.
A ground plane should be used, while the input impedance to
the part is kept as low as possible, to decrease parasitic
feedback. If the output board traces are longer than approxi-
mately half an inch, microstripline techniques must be em-
ployed to prevent ringing on the output waveform. Also, the
microstriplines must be terminated at the far end with the
characteristic impedance of the line to prevent reflections. All
supply voltage pins should be decoupled with high frequency
capacitors as close to the device as possible. All ground pins
should be connected to the same ground plane to further
improve noise immunity and shielding. If using the SPT9691
as a single comparator, the outputs of the inactive compara-
tor can be grounded, left open or terminated with 50 Ohms to
-2 V. All outputs on the active comparator, whether used or
unused, should have identical terminations to minimize
ground current switching transients.
Diode D1 connected between AVCC and GND is recom-
mended to prevent possible damage to the device in case
the AVCC supply is disconnected. The diode should be a
1N914 or equivalent. If AVCC is disconnected with this diode
in place, there will be approximately a 6 mA current draw
from both AVEE and DVEE. Diode D2 connected between
AVEE and DVEE is necessary to avoid power supply se-
quence latch-up. This diode keeps AVEE (also the substrate)
less than a silicon diode drop away from the most negative
circuit potential if DVEE is powered up first. This diode should
be a 1N5817 (Schottky) or equivalent.
Note: At no time should both inputs be allowed to float with
power applied to the device. At least one of the inputs should
be tied to a voltage within the common mode range (-4.0 to
+8.0 V) to prevent possible damage to the device. To prevent
possible latch-up during initial power up, the input voltages
should not exceed ±1 V. Additional protection diodes D3-D6
should be used on the inputs if there is the possibility of
exceeding the absolute maximum ratings of the inputs with
respect to AVCC and DVEE (1N914 or equivalent). NOTE: For
ease of implementation, all diodes (D1 - D6) can be 1N5817
(Schottky) or equivalent.
Figure 3 - SPT9691 Typical Interface Circuit
Figure 4 - SPT9691 Typical Interface Circuit With
Hysteresis
VIN
VREF
D3
D6
D4
D5
Noninverting Input
Inverting Input
AVEE DVEE AVCC GND
D1
D2
.1 µF .1 µF
.1 µF
D3
D6
+
-
LE
LE
ECL
Q Output
Q Output
VIN
VREF
RL
50 Ω
RL
50 Ω
-2 V
.1 µF
D4
D5
Noninverting Input
Inverting Input
= Represents line termination.
AVEE DVEE AVCC GND
D1
D2
.1 µF .1 µF
.1 µF
+
-
LE
LE
-1.3 V
100 Ω
.1 µF
Q Output
Q Output
RL
50 Ω
RL
50 Ω
-2 V
.1 µF
-2 V
= Represents line termination.
SPT9691
7
10/6/97
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