SPT7722 Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
SPT7722 Datasheet PDF : 12 Pages
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SPT7722
Pin Assignments
AGND
1
PD
2
CLK
3
CLK
4
RESET
5
RESET
6
OVDD
7
DGND
8
DA7 (MSB)
9
DA6
10
DA5
11
SPT7722
TOP VIEW
44L TQFP
33
AGND
32
DMODE1
31
DMODE2
30
OVDD
29
DGND
28
DCLKOUT
27
DCLKOUT
26
DB7 (MSB)
25
DB6
24
DB5
23
DB4
DATA SHEET
Pin Definitions
Pin Name
VIN+
VIN-
DA0–DA7
DB0–DB7
DCLKOUT
DCLKOUT
CLK
CLK
RESET
RESET
DMODE1,2
PD
VCM
AVCC
OVDD
AGND
DGND
Pin Number
40
39
16–9
19–26
28
27
4
3
5
6
32, 31
2
37
35, 36, 42, 43
7, 17, 30
1, 33, 34,
38, 41, 44
8, 18, 29
Pin Function Description
Non-Inverted Analog Input; nominally 1 VPP;
100k pullup to VCC and 100k pulldown to AGND, internally
Inverted Analog Input; nominally 1 VPP; 100k pullup to VCC and 100k
pulldown to AGND, internally
Data Output Bank A; 3V/5V LVCMOS compatible
Data Output Bank B; 3 V/5V LVCMOS compatible
Non-Inverted Data Output Clock; 3V/5V LVCMOS compatible
Inverted Data Output Clock; 3V/5V LVCMOS compatible
Non-Inverted Clock Input Pin; 100k pulldown to AGND, internally
Inverted Clock Input Pin; 17.5k pullup to VCC and 7.5k pulldown to AGND, internally
RESET synchronizes the data sampling and data output bank relationship when in
Dual Channel Mode (DMODE1 = 0); 100k pulldown to AGND, internally
Inverted RESET Input Pin; 17.5k pullup to VCC and 7.5 pulldown to AGND, internally
Internally:
100k pulldown to AGND on DMODE1
50k pullup to VCC on DMODE2
Data Output Mode Pins:
DMODE1 = 0, DMODE2 = 0: Parallel Dual Channel Output
DMODE1 = 0, DMODE2 = 1: Interleaved Dual Channel Output
DMODE1 = 1, DMODE2 = X: Single Channel Data Output on Bank A
(125 MSPS max)
Power Down Pin; PD = 1 for power-down mode. Outputs set to high impedance in
power-down mode; 100k pulldown to AGND, internally
2.5V Common Mode Voltage Reference Output
+5V Analog Supply
+3V/+5V Digital Output Supply
Analog Ground
Digital Ground
Rev. 1.0.2 December 2002
11
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