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SP810

3 Pin Microprocessor Supervisor Circuit

Signal Processing Technologies 

PIN DESCRIPTION

Pin Name

GND

RESET (SP809)

RESET (SP810)

VCC

Description

Ground.

Active low output pin. RESET Output remains low while VCC is below the reset

threshold.

Active high output pin. RESET Output remains high while VCC is below the reset

threshold.

Supply Voltage

µP will be activated at a valid reset state.

These µP supervisory circuits assert reset to

prevent code execution errors during power-

up, power-down, or brownout conditions.

Reset is guaranteed to be a logic low for

VTH>VCC>0.9V. Once VCC exceeded the reset

threshold, an internal timer keeps RESET low

for the reset timeout period; after this interval,

RESET goes high.

If a brownout condition occurs (V drops

CC

below the reset threshold), RESET goes low.

Any time VCC goes below the reset threshold,

the internal timer resets to zero, and RESET

goes low. The internal timer is activated after

VCC returns above the reset threshold, and

RESET remains low for the reset timeout

period.

Negative-Going VCC Transients

In addition to issuing a reset to the µP during

power-up, power-down, and brownout condi-

tions, SP809 series are relatively resistant to

short-duration negative-going VCC transient.

Ensuring a Valid Reset Output Down to

VCC= 0

When VCC falls below 0.9V, SP809 RESET

output no longer sinks current; it becomes

an open circuit. In this case, high-imped-

ance CMOS logic inputs connecting to

RESET can drift to undetermined voltages.

Therefore, SP809/810 with CMOS is

perfect for most applications of VCC down to

0.9V.

DETAILED DESCRIPTION

Benefits of Highly Accurate Reset

Threshold

SP809/810 with specified voltage as 5V±10%

or 3V±10% are ideal for systems using a

5V±5% or 3V±5% power supply. The reset is

guaranteed to assert after the power supply

falls below the minimum specified operating

voltage range of the system ICs. The

pretrimmed thresholds are reducing the range

over which an undesirable reset may occur.

APPLICATION INFORMATION

However in applications where RESET

must be valid down to 0V, adding a pull-

down resistor to RESET causes any

leakage currents to flow to ground, holding

RESET low.

Interfacing to µP with Bidirectional

Reset Pins

The RESET output on the SP809N is open

drain, this device interfaces easily with µPs

that have bidirectional reset pins. Connect-

ing the µP supervisor's RESET output

directly to the microcontroller's RESET pin

with a single pull-up resistor allows either

device to assert reset.

Date: 5/02/06 Rev B

SP809/810, 3 Pin Microprocessor Supervisor Circuit

5

© Copyright 2006 Sipex Corporation

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