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SP6651AEU-L/TR

High Efficiency 800mA Synchronous Buck Regulator

Signal Processing Technologies 

The SP6651A is a high efficiency synchronous

buck regulator with an input voltage range of

+2.7V to +5.5Vand an output that is adjustable

between +1.0V and VIN. The SP6651A features

a unique on-time control loop that runs in dis-

continuous conduction mode (DCM) or con-

tinuous conduction mode (CCM) using syn-

chronous rectification. Other features include

over-temperature shutdown, over-current pro-

tection, digitally controlled enable and under-

voltage lockout, a battery low indicator, and an

external feedback pin.

The SP6651A operates with a light load quies-

cent current of 20µA using a 0.3Ω PMOS main

switch and a 0.3Ω NMOS synchronous switch.

It operates with excellent efficiency across the

entire load range, making it an ideal solution for

battery powered applications and low current

step-down conversions. The part smoothly tran-

sitions into a 100% duty cycle under heavy load/

low input voltage conditions.

On-Time Control - Charge Phase

The SP6651A uses a precision comparator and

a minimum on-time to regulate the output volt-

age and control the inductor current under nor-

mal load conditions. As the feedback pin drops

below the regulation point, the loop comparator

output goes high and closes the main switch.

The minimum on-timer is triggered, setting a

logic high for the duration defined by:

TON =

KON

VIN - VOUT

where:

KON = 2.25V*µsec constant

VIN = VIN pin voltage

VOUT = VOUT pin voltage

To accommodate the use of ceramic and other

low ESR capacitors, an open loop ramp is added

to the feedback signal to mimic the inductor

current ripple. The following waveforms de-

scribe the ideal ramp operation in both CCM and

DCM operation.

In either CCM or DCM, the negative going

THEORY OF OPERATION

RAMP: CCM OPERATION

DRVON

I(L1)

FB’

REF, FB

VOS REF’

RAMP: DCM OPERATION

DRVON

I(L1)

FB’

REF’

REF, FB

VOS

ramp voltage (VRAMP in the functional diagram)

is added to FB and this creates the FB's signal.

This FB signal is applied to the negative termi-

nal of the loop comparator. To the positive

terminal of the loop comparator is applied the

REF voltage of 0.8V plus an offset voltage Vos

to compensate for the DC level of VRAMP ap-

plied to the negative terminal. The result is an

internal ramp with enough negative going offset

(approximately 50mV) to trip the loop com-

parator whenever FB falls below regulation.

The output of the loop comparator, a rising

VOLOW, causes a SET if BLANK = 0 and

OVR_I = 0. This starts inductor charging

(DRVON = 1) and starts the minimum on-timer.

The minimum on-timer times out and indicates

DRVON can be reset if the voltage loop is

satisfied. If VOUT is still below the regulation

Date: 5/25/04

SP6651A High Efficiency 800mA Synchronous Buck Regulator

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© Copyright 2004 Sipex Corporation

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