A
R
VOD
B
R VOC
Figure 1. Driver DC Test Load Circuit
Receiver
Output
Test Point
1KΩ
S1
VCC
CRL
1KΩ
S2
Figure 2. Receiver Timing Test Load Circuit
CL1
DI
A RL
B
CL2
A
RO
B
15pF
DI
A
B
A
RO
B
15pF
Figure 3a. Driver/Receiver Timing Test Circuit
Figure 3b. Timing Test Ckt. (V.35 mode only for SP504)
Output
Under
Test CL
500Ω
S1
VCC
S2
Figure 4. Driver Timing Test Load #2 Circuit
Note : Figures 3a and 3b shown above are used for evaluating maximum transmission rate. For 10Mbps transmission rate, an input signal of 5MHz is applied
to the driver input. In order for a valid transmission rate, the driver output must adhere to the output electrical specifications (VOH & VOL) and an
acceptable duty cycle for the protocol tested. The receiver outputs are checked for proper TTL/CMOS VOH & VOL levels and an acceptable output
duty cycle.
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
© Copyright 2004 Sipex Corporation
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