LC83010N Ver la hoja de datos (PDF) - SANYO -> Panasonic

Número de pieza

componentes Descripción

Fabricante

LC83010N

Audio Digital Signal Processor

SANYO -> Panasonic 

LC83010N, 83010NE

Specifications

Absolute Maximum Ratings at Ta = 25˚C, VSS = 0V

Parameter

Symbol

Maximum supply voltage

VDDmax

Conditions

Output voltage

Input voltage

Peak output current

Average output current

Allowable power dissipation

Operating temperature

Storage temperature

V01

V02

VIN

IOP1

IOP2

IOP3

IOA1

IOA2

IOA3

IOA4

∑ IOA1

∑ IOA2

∑ IOA3

∑ IOA4

Pd max

Topr

Tstg

OSC2 output

Pins except for the OSC2

Audio I/F, DRAM I/F

Microcomputer I/F

P0 to P5

Audio I/F: Per pin

Audio I/F, DRAM I/F: Per pin

Microcomputer I/F: Per pin

P0 to P5: Per pin

Audio I/F: Total

Audio I/F, DRAM I/F: Total

Microcomputer I/F: Total

P0 to P5: Total

Ta=–30 to +70˚C

* When soldering QFP devices, do not use the solder dip method.

Ratings

Unit

– 0.3 to +7.0 V

Up to the voltage

produced by

V

oscillation

– 0.3 to VDD +0.3 V

– 0.3 to VDD +0.3 V

– 2 to +4 mA

– 2 to +10 mA

– 0.5 to +10 mA

– 2 to +4 mA

– 2 to +4 mA

– 2 to +10 mA

– 0.5 to +10 mA

– 11 to +45 mA

– 4 to +15 mA

4 to +15 mA

– 3 to +30 mA

600 mW

– 30 to +70 ˚C

– 40 to +125 ˚C

Note

1

2

3

4

5

2

3

4

5

2

3

Allowable Operating Conditions at Ta = –30 to +70˚C, VDD = 4.75V to 5.25V, VSS = 0V, unless otherwise noted

Parameter

Symbol

Conditions

Ratings

min

typ

max

Unit Note

Operating supply voltage

Input high-level voltage

Input low-level voltage

Operating frequency (Instruction cycle time)

VDD

VIH1

VIH2

VIH3

VIL1

VIL2

VIL3

fOP

(TCYC)

Audio I/F, DRAM I/F

P0 to P5, SELC, TEST1 to 4

RES, INT, Microcomputer I/F

Audio I/F, DRAM I/F

P0 to P5, SELC, TEST1 to 4

RES, INT, Microcomputer I/F

Up to 1% crystla oscillation error is allowed.

max: 48kHz × 384 × 1.01

4.75

2.4

0.7VDD

0.75VDD

12.17

(165)

5.25 V

V

6

V

V

7

0.8 V

6

0.3VDD V

0.25VDD V

7

18.62 MHz

(107)ns (ns)

Frequency

fEXT

12.17

18.62 MHz

Pulse width

Rise time

Fall time

fEXTH

fEXTL

fEXTR

fEXTF

Applies to the OSC1 pin.

See figure 1.

(OSC1: input, OSC2: open)

20

ns

10 ns

oscillation frequency

fEXT OSC1, OSC2, See figure 2.

18.62 MHz

oscillation stablizing period

Transfer bit clock cycle

Transfer bit clock pulse width

Data set up time

Data hold time

fEXTS See figure 3.

tBCYC

tBCW

tS

Applies to the BCK1 and BCK2 pins.

See figure 4.

tH

ms

325

ns

100

ns

75

ns

75

ns

Continued on next page.

No.3945–6/18

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