SPT9210SCS Ver la hoja de datos (PDF) - Signal Processing Technologies
Número de pieza
componentes Descripción
Fabricante
SPT9210SCS Datasheet PDF : 11 Pages
| |||
SPT VIDEO CHIP SET APPLICATION
The SPT9210 is the front-end analog video processor for the
SPT NTSC/PAL video decoder chip set. This chip set, as
shown in figure 1, is comprised of three monolithic chips, which
together provide an overall integrated video decoding function-
ality at 8.9 effective number of bits of dynamic performance.
The full set includes the SPT9210 analog video processor,
the SPT7852 dual 10-bit analog-to-digital converter and the
SPT2110 NTSC/PAL video decoder. The SPT9210 is specifi-
cally designed to process video input signals so as to attain
optimal data conversion by the SPT7852 analog-to-digital
converter. Data sheets describing the overall chip set and the
other components are available by contacting the factory.
SPT9210 GENERAL DESCRIPTION
The SPT9210 is a fully integrated analog video processor
chip capable of processing standard video signals in either a
single-channel composite video input mode or a dual-chan-
nel S-Video input mode. Standard 1 VP-P video signals are
amplified to match the optimal drive requirements of the
SPT7852 dual 10-bit analog-to-digital converter.
INPUT SELECTION
As the typical interface circuit shows in figure 3, the mux
selector pin (pin 1) controls selection between composite and
S-Video (component Y/C). This is a TTL-level input. When
composite video is selected (pin 1 high), the composite signal
(pin 19) is fed into the luminance channel, and the chromi-
nance channel is internally biased (i.e., no input is sourced).
When S-Video is selected (pin 1 low), the S-Video luminance
signal (pin 2) is fed into the luminance channel, and the S-
Video chrominance signal (pin 3) is fed into the chrominance
channel.
In addition to pin 19, another composite video signal can be
applied to input pin 2. Pin 1 selects which video signal is to be
processed. (Pin 1 high selects input from pin 19.) When
operating with composite video on pin 2, decouple pin 3 to
ground with a 0.1 µF capacitor (the chrominance input for S-
video). This will reduce the noise produced on this input.
A register or TTL buffer can drive pin 1 (video select switch).
An optional transistor circuit is shown in figure 3. It is driven
by the pin 1 signal with the collector tied to pin 3. It is used to
reduce crosstalk that may occur when both composite and S-
Video signals are operating simultaneously. The transistor
circuit is only necessary if both signals are present.
All input video signals should be terminated with 75 Ω
resistors and AC coupled to the SPT9210 with a 0.47 µF
capacitor.
INTERNAL CLAMP, BIAS AND SYNC DETECTION
The signals fed into the luminance channel (pins 2 and 19),
which are either a composite signal or a luminance (Y) signal,
are internally DC restored to 2.0 V by an internal clamp circuit.
Note that this is not the final output clamp voltage as dis-
cussed in the Final DC Clamp and Gain Stages section. The
chrominance signal (pin 3) is biased to 2.5 V by an internal
bias circuit.
The luminance signal path has a sync separation circuit that
compares the sync signal to a detection threshold and
generates internal gain control and output clamping control
signals. These timing signals are used to control internal
sampling of the sync tip amplitude by the automatic gain
control circuit. (See the Automatic Gain Control discussion.)
Figure 1 - SPT Video Decoder Chip Set
SPT9210
Select
Composite
Video Signal
M
u
S-Video
x
Y Signal
Bias
Ext Adj
5
Clamp
LPF
AGC
M
Clamp
u
LPF
S-Video
x
AGC
C Signal
ADC VRef
SPT7852
Output Enable
SPT2110
10-Bit ADC
B9
u
f
Sync Det
Trap Filter
M
u
Y/C Separator
x
(Comb)
M
B9
u
10-Bit ADC
u
x
f
Pixel Clock
Luma
Processing
Chroma
Processing
2
Ref
Ladder
Timing
Control Parameter
Registers
Timing Generation
2X Clock Reset
13
MPU Interface
Reset
8
RY
8
G Cr/Cb
8
B
5
HSYNC
VSYNC
HBLNK
VBLNK
ODD
SPT
3
SPT9210
11/7/97
Share Link: 