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AN87C196CA18

Advanced 16-Bit CHMOS Microcontroller

Intel 

87C196CA 18 MHz Microcontroller — Automotive

Table 2.

Pin Descriptions (Sheet 1 of 2)

VCC

VSS

Symbol

VREF

VPP

ANGND

XTAL1

XTAL2

P2.7/CLKOUT

RESET#

NMI

EA#

P5.0/ALE/ADV#

P5.3/RD#

P5.2/WR#/WRL#

P5.5/BHE#/WRH#

Name and Function

Main supply voltage (+5 V).

Digital circuit ground (0 V). There are three VSS pins, all of which MUST be

connected to a single ground plane.

Reference for the A/D converter (+5 V). VREF is also the supply voltage to the

analog portion of the A/D converter and the logic used to read Port 0. Must be

connected for A/D and Port 0 to function.

Programming voltage for the EPROM parts. It should be +12.5 V for programming.

It is also the timing pin for the return from powerdown circuit. Connect this pin with

a 1 µF capacitor to VSS and a 1 MΩ resistor to VCC. If this function is not used, VPP

may be tied to VCC.

Reference ground for the A/D converter. Must be held at nominally the same

potential as VSS.

Input of the oscillator inverter and the internal clock generator.

Output of the oscillator inverter.

Output of the internal clock generator. The frequency is ½ the oscillator frequency.

It has a 50% duty cycle. Also LSIO pin when not used as CLKOUT.

Reset input to the chip. Input low for at least 16 state times will reset the chip. The

subsequent low to high transition resynchronizes CLKOUT and commences a 10-

state time sequence in which the PSW is cleared, bytes are read from 2018H and

201AH loading the CCBs, and a jump to location 2080H is executed. Input high for

normal operation. RESET# has an internal pullup.

A positive transition causes a non-maskable interrupt vector through memory

location 203EH.

Input for memory select (External Access). EA# equal to a high causes memory

accesses within the [EP]ROM address space to be directed to on-chip EPROM/

ROM. EA# equal to a low causes accesses to these locations to be directed to off-

chip memory. EA# = +12.5 V causes execution to begin in the Programming

Mode. EA# latched at reset.

Address Latch Enable or Address Valid output, as selected by CCR. Both pin

options provide a latch to demultiplex the address from the address/data bus.

When the pin is ADV#, it goes inactive (high) at the end of the bus cycle. ADV#

can be used as a chip select for external memory. ALE/ADV# is active only during

external memory accesses. Also LSIO when not used as ALE.

Read signal output to external memory. RD# is active only during external memory

reads. LSIO when not used as RD#.

Write and Write Low output to external memory, as selected by the CCR, WR# will

go low for every external write, while WRL# will go low only for external writes

where an even byte is being written. WR#/WRL# is active during external memory

writes. Also an LSIO pin when not used as WR#/WRL#.

Byte High Enable or Write High output, as selected by the CCR. BHE# = 0 selects

the bank of memory that is connected to the high byte of the data bus. A0 = 0

selects that bank of memory that is connected to the low byte. Thus accesses to a

16-bit wide memory can be to the low byte only (A0 = 0, BHE# =1), to the high byte

only (A0 = 1, BHE# = 0) or both bytes (A0 = 0, BHE# = 0). If the WRH# function is

selected, the pin will go low if the bus cycle is writing to an odd memory location.

BHE#/WRH# is only valid during 16-bit external memory write cycles. Also an

LSIO pin when not BHE#/WRH#.

6

Datasheet

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