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AN87C196CB-20 Ver la hoja de datos (PDF) - Intel

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AN87C196CB-20 Datasheet PDF : 33 Pages
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87C196CA 87C196CB
Symbol
VCC
VSS VSS1
VREF
ANGND
VPP
XTAL1
XTAL2
RESET
NMI
EA
PLLEN
(196CB only)
P6 4–6 7 SSIO
P6 3 T1DIR
(CB only)
P6 2 T1CLK
(CB only)
P6 0–6 1 EPA8– 9
Name and Function
Main Supply Voltage (a5V)
Digital circuit ground (0V) There are 7 VSS pins CB (4 on CA) all of which MUST be
connected to a single ground plane
Reference for the A D converter (a5V) VREF is also the supply voltage to the analog
portion of the A D converter and the logic used to read Port 0 Must be connected for
A D and Port 0 to function
Reference ground for the A D converter Must be held at nominally the same potential
as VSS
Programming voltage for EPROM parts It should be a12 5V for programming It is
also the timing pin for the return from powerdown circuit Connect this pin with a 1 mF
capacitor to VSS and a 1Mohm resistor to VCC If this function is not used VPP may be
tied to VCC
Input of the oscillator inverter and the internal clock generator
Output of the Oscillator Inverter
Reset input to the chip Input low for at least 16 state times will reset the chip The
subsequent low to high transition resynchronizes CLKOUT and commences a
10-state time sequence in which the PSW is cleared bytes are read from 2018H
201Ah and 201CH (if enabled) loading the CCB’s and a jump to location 2080H is
executed Input high for normal operation RESET has an internal pullup
A positive transition causes a non-maskable interrupt vector through memory location
203EH If not used this pin should be tied to VSS May be used by Intel Evaluation
boards
Input for memory select (External Access) EA equal to a high causes memory
accesses to locations 0FF2000H through 0FFFFFFH to be directed to on-chip
EPROM ROM EA equal to a low causes accesses to these locations to be directed
to off-chip memory EA e a12 5V causes execution to begin in the Programming
Mode EA is latched at reset
Selects between PLL mode or PLL bypass mode This pin must be either tied high or
low PLLEN pin e 0 bypass PLL mode PLLEN pin e 1 places a 4x PLL at the input
of the crystal oscillator Allows for a low frequency crystal to drive the device (i e
5 MHz e 20 MHz operation)
Dual function I O ports have a system function as Synchronous Serial I O Two pins
are clocks and two pins are data providing for full duplex capability Also LSIO when
not used as SSIO
Dual function I O pin Primary function is that of a bidirectional I O pin however it
may also be used as a TIMER1 Direction input The TIMER1 will increment when this
pin is high and decrements when this pin is low
Dual function I O pin Primary function is that of a bidirectional I O pin however may
also be used as a TIMER1 Clock input The TIMER1 will increment or decrement on
both positive and negative edges of this pin
Dual function I O port pins Primary function is that of bidirectional I O System
function is that of High Speed capture and compare
7

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