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MX29F001TTC-12

1M-BIT [128K x 8] CMOS FLASH MEMORY

Macronix International 

MX29F001T/B

AUTOMATIC PROGRAMMING

The MX29F001T/B is byte programmable using the

Automatic Programming algorithm. The Automatic

Programming algorithm does not require the system to

time out or verify the data programmed. The typical

chip programming time of the MX29F001T/B at room

temperature is less than 3.5 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase

pulses according to MXIC's Automatic Chip Erase

algorithm. Typical erasure at room temperature is

accomplished in less than 3 second. The Automatic

Erase algorithm automatically programs the entire

array prior to electrical erase. The timing and

verification of electrical erase are internally controlled

within the device.

AUTOMATIC SECTOR ERASE

The MX29F001T/B is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle. The

Automatic Sector Erase algorithm automatically pro-

grams the specified sector(s) prior to electrical erase.

The timing and verification of electrical erase are inter-

nally con trolled by the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires

the user to only write program set-up commands

(include 2 unlock write cycle and A0H) and a program

command (program data and address). The device

automatically times the programming pulse width,

provides the program verification, and counts the

number of sequences. A status bit similar to DATA

polling and a status bit toggling between consecutive

read cycles, provides feedback to the user as to the

status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stand-

ard microprocessor write timings. The device will

automatically pre-program and verify the entire array.

Then the device automatically times the erase pulse

width, provides the erase verification, and counts the

number of sequences. A status bit toggling between

consecutive read cycles provides feedback to the user

as to the status of the programming operation.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming

circuitry. During write cycles, the command register

internally latches addresses and data needed for the

programming and erase operations. During a system

write cycle, addresses are latched on the falling edge,

and data are latched on the rising edge of WE .

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness. The MX29F001T/B electri-

cally erases all bits simultaneously using Fowler-Nord-

heim tunneling. The bytes are programmed by using the

EPROM programming mechanism of hot electron

injection.

During a program cycle, the state-machine will control the

program sequences and command register will not re-

spond to any command set. During a Sector Erase cycle,

the command register will only respond to Erase Suspend

command. After Erase Suspend is completed, the device

stays in read mode. After the state machine has com-

pleted its task, it will allow the command register to

respond to its full command set.

P/N: PM0515

REV. 2.1, JUN. 14, 2001

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