MX29F001BPC-12 Ver la hoja de datos (PDF) - Macronix International
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MX29F001BPC-12 Datasheet PDF : 43 Pages
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MX29F001T/B
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will not
initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE must
be a logical zero while OE is a logical one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between its VCC and GND. (Using a 10uF bulk capacitor
connected for high current condition is available if
necessary.)
CHIP PROTECTION WITH 12V SYSTEM
The MX29F001T/B features hardware chip protection.
which will disable both program and erase operations. To
activate this mode, the programming equipment must
force VID on address pin A9 and control pin OE, (suggest
VID=12V) A6=VIL and CE=VIL.(see Table 2) Programming
of the protection circuitry begins on the falling edge of the
WE pulse and is terminated with the rising edge of the
same. Please refer to chip protect algorithm and waveform.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for the
protected status. Otherwise the device will produce 00H
for the unprotected status. In this mode, the address,except
for A1, are don't care. Address locations with A1 = VIL are
reserved to read manufacturer and device codes.(Read
Silicon ID)
It is also possible to determine if the chip is protected in
the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected status.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F001T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect completion to incorporate any changes in the
code.
To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and waveform
for the chip unprotect algorithm. The unprotection
mechanism begins on the falling edge of the WE pulse
and is terminated with the rising edge of the same.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs (Q0-Q7) for an unprotected sector. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
CHIP PROTECTION WITHOUT 12V SYSTEM
The MX29F001T/B also feature a hardware chip protection
method in a system without 12V power suppply. The
programming equipment do not need to supply 12 volts to
protect all sectors. The details are shown in chip protect
algorithm and waveform.
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F001T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and waveform.
POWER-UP SEQUENCE
The MX29F001T/B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command
sequences.
P/N: PM0515
REV. 2.1, JUN. 14, 2001
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