SMH4802S(2009) Ver la hoja de datos (PDF) - Summit Microelectronics
Número de pieza
componentes Descripción
Fabricante
SMH4802S
(Rev.:2009)
(Rev.:2009)
Summit Microelectronics
SMH4802S Datasheet PDF : 19 Pages
| |||
SMH4802
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS
Symbol
Parameter
fSCL
tLOW
tHIGH
tBUF
tSU:STA
tHD:STA
tSU:STO
t
AA
tDH
tR
tF
tSU:DAT
tHD:DAT
TI
SCL clock frequency
Clock low period
Clock high period
Bus free time
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to valid output
Data Out hold time
SCL and SDA rise time
SCL and SDA fall time
Data In setup time
Data In hold time
Noise filter SCL and SDA
tWR
Write cycle time
Conditions
Before new transmission
SCL low to valid SDA (cycle n)
SCL low (cycle n + 1) to SDA change
Min.
0
4.7
4.0
4.7
4.7
4.0
4.7
0.2
0.2
250
0
Noise suppression
Max.
100
3.5
1000
300
100
5
Units
kHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ms
2062 Intf. Table
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS
Figure 3 shows a timing diagram for the Bus Interface Memory timing. One bit of data is transferred during each
clock pulse. Note that data must remain stable when the clock is high.
tR
SCL
tF
tHIGH
tLOW
tSU:SDA
SDA In
tHD:SDA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tAA
tDH
SDA Out
SUMMIT MICROELECTRONICS, Inc.
Figure 3. Bus Interface Memory Timing
2062 2.4 03/27/09
2050 Fig09 2.0
7
Share Link: