SMH4802S(2009) Ver la hoja de datos (PDF) - Summit Microelectronics

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SMH4802S
(Rev.:2009)

Programmable -48V Hot-Swap Controller with Forced Shut Down

Summit Microelectronics 

SMH4802

Preliminary Information

GENERAL DESCRIPTION

The SMH4802 is an integrated power controller for hot

swappable add-in cards. The device operates from a wide

supply range and generates the signals necessary to

drive an isolated output DC/DC converter. As a typical

add-in board is inserted into the powered backplane,

physical connections must first be made with the chassis

to discharge any electrostatic voltage potentials. The

board then contacts the long pins on the backplane that

provide power and ground. As soon as power is applied,

the device starts up, but does not immediately apply

power to the output load. Under-voltage and over-voltage

circuits inside the controller verify the input voltage is

within the user-specified range.

Once these requirements are met, the hot-swap controller

enables VGATE to turn on the external power MOSFET.

The VGATE output is current limited to IVGATE, allowing the

slew rate to be easily modified using external passive

components. During the controlled turn-on period the VDS

of the MOSFET is monitored by the DRAIN SENSE input.

When DRAIN SENSE drops below 2.5V, and VGATE is

greater than VDD – VGT, the PG# output can begin turning

on the DC/DC converter.

Steady state operation is maintained as long as all

conditions are normal. Any of the following events may

cause the device to disable the DC/DC controller by

shutting down the power MOSFET: an under-voltage or

over-voltage condition on the host power supply; an over-

current event detected on the CBSENSE input; a failure

of the power MOSFET sensed via the DRAIN SENSE pin;

the master enable (EN/TS) falling below 2.5V; or the FS#

input being driven low by events on the secondary side of

the DC/DC controller. If one of these events occurs the

SMH4802 can be configured so VGATE shuts off and

either latches into an off state or recycles power after a

cooling down period, tCYC.

FUNCTIONAL BLOCK DIAGRAM

VDD 14

12VREF

+

DRAIN

SENSE 1

–

EN/TS 3

UV 8

OV 9

5V

VSS 7

Prog.

Ref.

12V

200kΩ

+

–

+

–

+

–

2.5V

OV/UV

FILTER

SCL 5

SDA 4

50kΩ

50kΩ

I2C INTERFACE

LOGIC

PROGRAMM-

ABLE

DELAY

PROGRAMMABLE

SHUTDOWN

TIMER

10 FS#

11 5.0VREF

PROGRAMM-

ABLE

DELAY

12 PG#

VGATE

SENSE

2 VGATE

CBSENSE 6

2

PROGRAMMED

DELAY

+

50mV

–

+

PROGRAMMED –

Quick-Trip

DUTY

CYCLE

TIMER

2062 BD

Figure 2. Functional Block diagram. Pin numbers reflect SOIC package.

2062 2.4 03/27/09

SUMMIT MICROELECTRONICS, Inc.

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