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SI5330L-A00230-GM

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Silicon Laboratories 

Si5330

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW

CLOCK BUFFER/LEVEL TRANSLATOR

Features

 Supports single-ended or

differential input clock signals

 Generates four differential

(LVPECL, LVDS, HCSL) or eight

single-ended (CMOS, SSTL,

HSTL) outputs

 Provides signal level translation

Differential to single-ended

Single-ended to differential

Differential to differential

Single-ended to single-ended

 Wide frequency range

LVPECL, LVDS: 5 to 710 MHz

HCSL: 5 to 250 MHz

SSTL, HSTL: 5 to 350 MHz

CMOS: 5 to 200 MHz

 Additive jitter: 150 fs RMS typ

 Output-output skew: 100 ps

 Propagation delay: 2.5 ns typ

 Single core supply with excellent

PSRR: 1.8, 2.5, or 3.3 V

 Output driver supply voltage

independent of core supply: 1.5,

1.8, 2.5, or 3.3 V

 Loss of Signal (LOS) indicator

allows system clock monitoring

 Output Enable (OEB) pin allows

glitchless control of output clocks

 Low power: 10 mA typical core

current

 Industrial temperature range:

–40 to +85 °C

 Small size: 24-lead, 4 x 4 mm

QFN

Applications

 High Speed Clock Distribution

 Ethernet Switch/Router

 SONET / SDH

 PCI Express 2.0/3.0

 Fibre Channel

 MSAN/DSLAM/PON

 Telecom Line Cards

Ordering Information:

See page 14.

Pin Assignments

IN1

IN2

IN3

RSVD_GND

RSVD_GND

RSVD_GND

24 23 22 21 20 19

GND

GND

7 8 9 10 11 12

CLK1A

CLK1B

VDDO1

VDDO2

CLK2A

CLK2B

Functional Block Diagram

VDD

Si5330

VDDO0

CLK0

Single-ended

IN

or

Differential

VDDO1

CLK1

VDDO2

CLK2

Single-ended

or

Differential

LOS

OEB

Control

VDDO3

CLK3

Rev. 1.0 4/12

Copyright © 2012 by Silicon Laboratories

Si5330

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