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SI4702-C19-GM Ver la hoja de datos (PDF) - Silicon Laboratories

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SI4702-C19-GM
Silabs
Silicon Laboratories Silabs
SI4702-C19-GM Datasheet PDF : 46 Pages
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Si4702/03-C19
Table 4. Reset Timing Characteristics (Busmode Select Method 1)1,2,3
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
RSTpulse width and GPIO3 Setup tGSRST14
to RST
GPIO3 = 0
100
µs
SEN and SDIO Setup to RST
tSRST1
30
ns
SEN, SDIO, and GPIO3 Hold from
RST
tHRST1
30
ns
Notes:
1. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the 1st start condition.
4. If GPIO3 is driven low by the user, then minimum tGSRST1 is only 30 ns. If GPIO3 is hi-Z, then minimum tGSRST1 is
100 µs, to provide time for an on-chip 1 Mpulldown device (active while RST is low) to discharge the pin.
70%
RST
30%
tGSRST1
tHRST1
70%
GPIO3
30%
tSRST1
SEN, 70%
SDIO 30%
Figure 1. Reset Timing Parameters for Busmode Select Method 1 (GPIO3 = 0)
6
Rev. 1.1

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