SFH6318T Ver la hoja de datos (PDF) - Siemens AG
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SFH6318T Datasheet PDF : 3 Pages
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Electro-Optical Characteristics (TA=0°C to 70°C, TA=25°C-Typical, unless otherwise specified)
Parameter
Symbol Device
Min Typ Max Units Test Conditions
Note
Current Transfer Ratio
Logic Low
Output Voltage
Logic High
Output Current
Logic Low Supply Current
Logic High Supply Current
Input Forward Voltage
Temperature Coefficient,
Forward Voltage
Input Capacitance
Resistance (Input-Output)
Capacitance (Input-Output)
CTR
SFH6318T 300
SFH6319T 400
500
VOL
SFH6318T
SFH6319T
IOH
SFH6318T
SFH6319T
ICCL
ICCH
VF
∆VF/∆TA
CIN
RI-O
CI-O
1600 2600 %
1600 2600 %
2000 3500
0.1 0.4 V
0.1 0.4 V
0.15 0.4
0.25 0.4
0.1 250 µA
0.05 100 µA
0.2 1.5 mA
0.01 10 µA
1.4 1.7 V
–1.8
mV/
°C
25
pF
1012
Ω
1011
Ω
0.6
pF
IF=1.6 mA, VO=0.4 V, VCC=4.5 V 1,2
IF=0.5 mA, VO=0.4 V, VCC=4.5 V 1,2
IF=1.6 mA, VO=0.4 V, VCC=4.5 V
IF=1.6 mA, IO=4.8 mA, VCC=4.5 V 2
IF=1.6 mA, IO=8 mA, VCC=4.5 V 2
IF=5 mA, IO=15 mA, VCC=4.5 V
IF=12 mA, IO=24 mA, VCC=4.5 V
IF=0 mA, VO=VCC=7 V
2
IF=0 mA, VO=VCC=18 V
2
IF=1.6 mA, VO=OPEN, VCC=18 V 2
IF=0 mA, VO=OPEN, VCC=18 V
2
IF=1.6 mA, TA=25°C
IF=1.6 mA
f=1 MHz, VF=0
VIO=500 VDC, TA=25°C
3
VIO=500 VDC, TA=100°C
f=1 MHz
3
Switching Specifications (TA=25°C)
Parameter
Symbol Device
Min Typ
Max Units Test Conditions
Note
Propagation Delay Time
To Logic Low at Output
tPHL
SFH6318T
SFH6319T
Propagation Delay Time
To Logic High at Output
tPLH
SFH6318T
SFH6319T
Common Mode Transient Im-
munity at Logic High Level
Output
| CMH |
2
10
µs
IF=1.6 mA, RL=2.2 KΩ
6
25
µs
IF=0.5 mA, RL=4.7 KΩ
2,4
0.6
1
IF=12 mA, RL=270 Ω
2
35
µs
IF=1.6 mA, RL=2.2 KΩ
4
60
µs
IF=0.5 mA, RL=4.7 KΩ
2,4
1.5
7
IF=12 mA, RL=270 Ω
1K
V/µs
IF=0 mA, RL=2.2 KΩ
5,6
VCM=10 Vp-p
Common Mode Transient Im-
munity at Logic Low Level Out-
put
| CML|
1K
V/µs
IF=1.6 mA, RL=2.2 KΩ
5,6
VCM=10 Vp-p
Notes
1. DC current transfer ratio is defined as the ratio of outpput collector current, IO, to the forward LED input current, IF times 100%.
2. Pin 7 open.
3. Device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together.
4. Using a resistor between pin 5 and 7 will decrease gain and delay time.
5. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the commo-
mode pulse, VCM, to assure that the output will remain in a logic high state (i.e. VO>2.0 V) common mode transient immunity in logic
low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode puse signal, VCM, to assure that the
output will remain in a logic low state (i.e. VO<0.8 V).
6. In applications where dv/dt may exceed 50,000 V/µs (such as state discharge) a series resistor, RCC should be included to protect IC
from destructively high surge currents. The recommended value is RCC≅
IV kΩ. Refer to Figure 2.
0.15 IF(mA)
Semiconductor Group
4–49
SFH6318T/6319T
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