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WF2M32-90G2UC5

2Mx32 5V Flash Module

White Electronic Designs => Micro Semi 

White Electronic Designs

WF2M32-XXX5

2Mx32 5V Flash Module

FEATURES

Access Time of 90, 120, 150ns

Packaging:

• 66 pin, PGA Type, 1.185" square, Hermetic

Ceramic HIP (Package 401).

• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880")

square (Package 510) 3.56mm (0.140") height.

Designed to fit JEDEC 68 lead 0.990" CQFJ

footprint (FIGURE 3)

Sector Architecture

• 32 equal size sectors of 64KBytes per each 2Mx8

chip

• Any combination of sectors can be erased. Also

supports full chip erase.

Minimum 100,000 Write/Erase Cycles Minimum

Organized as 2Mx32

Commercial, Industrial, and Military

Temperature Ranges

5 Volt Read and Write. 5V ± 10% Supply.

Low Power CMOS

Data# Polling and Toggle Bit feature for detection of

program or erase cycle completion.

Supports reading or programming data to a sector

not being erased.

RESET# pin resets internal state machine to the

read mode.

Built in Decoupling Caps and Multiple Ground Pins

for Low Noise Operation, Separate Power and

Ground Planes to improve noise immunity

* This product is subject to change without notice.

Note: For programming information refer to Flash Programming 16M5 Application Note.

FIGURE 1 – PIN CONFIGURATION FOR WF2M32-XHX5

Top View

1

12

23

I/O8

WE2# I/O15

34

45

56

I/O24

VCC

I/O31

I/O9

CS2#

I/O14

I/O25

CS4#

I/O30

I/O10

GND

I/O13

I/O26 WE4#

I/O29

A14

I/O11

I/O12

A7

I/O27

I/O28

A16

A10

OE#

A12

A4

A1

A11

A9

A17

A20

A5

A2

A0

A15

WE1#

A13

A6

A3

A18

VCC

I/O7

A8 WE3#

I/O23

I/O0

CS1#

I/O6

I/O16

CS3#

I/O22

I/O1

A19

I/O5

I/O17

GND

I/O21

I/O2

I/O3

I/O4

11

22

33

I/O18

I/O19

I/O20

44

55

66

Pin Description

I/O0-31 Data Inputs/Outputs

A0-20 Address Inputs

WE1-4# Write Enables

CS1-4# Chip Selects

OE#

Output Enable

VCC

Power Supply

GND

Ground

OE#

A0-20

Block Diagram

WE1# CS1#

WE2# CS2#

WE3# CS3#

2M x 8

2M x 8

2M x 8

WE4# CS4#

2M x 8

8

I/O0-7

8

I/O8-15

8

I/O16-23

8

I/O24-31

RESET# internally tied to VCC in the HIP package for this pin con-

figuration. See Alternate Pin Configuration with RESET# tied to pin

12 for system control of reset (FIGURE 10, page 11).

October 2004

Rev. 5

1

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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