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MU9C1480A

MU9C1480A/L LANCAMs®

Music Semiconductors 

MU9C1480A/L Draft

FUNCTIONAL DESCRIPTION Continued

related to the destination or source address information register’s contents are reset, enable or disable Match flag,

held in the CAM subfield of a given location. In a translation enable or disable Full flag, CAM/RAM partitioning, disable

application, the CAM field could hold the dictionary entries, or select masking conditions, disable or select

while the RAM field holds the translations, with almost auto-incrementing or auto-decrementing the Address

instantaneous response.

register, and select Standard or Enhanced mode. The active

Segment Control register contains separate counters to

Each entry has two validity bits (known as Skip bit and control the writing of 16-bit data segments to the selected

Empty bit) associated with it to define its particular type: persistent destination, and to control the reading of 16-bit

Empty, Valid, Skip, or RAM. When data is written to the data segments from the selected persistent source.

active Comparand register, and the active Segment Control

register reaches its terminal count, the contents of the There are two active mask registers at any one time, which

Comparand register are automatically compared with the can be selected to mask comparisons or data writes. Mask

CAM portion of all the valid entries in the memory array. Register 1 has both a foreground and background mode to

For added versatility, the Comparand register can be support rapid context switching. Mask Register 2 does not

barrel-shifted right or left one bit at a time. A Compare have this mode, but can be shifted left or right one bit at a

instruction then can be used to force another compare time. For masking comparisons, data stored in the active

between the Comparand register and the CAM portion of selected mask register determines which bits of the

memory entries of any one of the four validity types. After comparand are compared against the valid contents of the

a Read or Move from Memory operation, the validity bits memory. If a bit is set HIGH in the mask register, the same

of the location read or moved will be copied into the Status bit position in the Comparand register becomes a “don’t

register, where they can be read using Command care” for the purpose of the comparison with all the memory

Read cycles.

locations. During a Data Write cycle or a MOV instruction,

Data can be moved from one of the data registers (CR, data in the specified active mask register can also determine

MR1, or MR2) to a memory location that is based on the which bits in the destination will be updated. If a bit is

results of the last comparison (Highest-Priority Match or HIGH in the mask register, the corresponding bit of the

Next Free), or to an absolute address, or to the location destination is unchanged.

pointed to by the active Address register. Data can also be

written directly to the memory from the DQ bus using any The match line associated with each memory address is fed

of the above addressing modes. The Address register may into a priority encoder where multiple responses are

be directly loaded and may be set to increment or resolved, and the address of the highest-priority responder

decrement, allowing DMA-type reading or writing from (the lowest numerical match address) is generated. In LAN

memory.

applications, a multiple response might indicate an error. In

other applications the existence of multiple responders may

Two sets of configuration registers (Control, Segment be valid.

Control, Address, Mask Register 1, and Persistent Source

and Destination) are provided to permit rapid context Four input control signals and commands loaded into an

switching between foreground and background activities. instruction decoder control the LANCAM. Two of the four

The currently active set of configuration registers controls input control signals determine the cycle type. The control

writes, reads, moves, and compares. The foreground set signals tell the device whether the data on the I/O bus

typically would be pre-loaded with values useful for represents data or a command, and is input or output.

comparing input data, often called filtering, while the Commands are decoded by instruction logic and control

background set would be pre-loaded with values useful for moves, forced compares, validity bit manipulations, and

housekeeping activities such as purging old entries. the data path within the device. Registers (Control, Segment

Moving from the foreground task of filtering to the Control, Address, Next Free Address, etc.) are accessed

background task of purging can be done by issuing a single using Temporary Command Override instructions. The data

instruction to change the current set of configuration path from the DQ bus to/from data resources (comparand,

registers. The match condition of the device is reset masks, and memory) within the device are set until changed

whenever the active register set is changed.

by Select Persistent Source and Destination instructions.

The active Control register determines the operating

conditions within the device. Conditions set by this

After a Compare cycle (caused by either a data write to the

Comparand or mask registers, a write to the Control register,

5

Rev. 3.0 Draft

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