QL4090-2CF208C Ver la hoja de datos (PDF) - QuickLogic Corporation
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QL4090-2CF208C Datasheet PDF : 18 Pages
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QL4009 QuickRAM Data Sheet Rev C
Symbol
RPDRD
Table 4: RAM Cell Asynchronous Read Timing
Parameter
Propagation Delays (ns)
Fanout
RA to RDa
1
2
3
4
5
3.0 3.3 3.6 3.9 5.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
Symbol
tIN
tINI
tISU
tIH
tICLK
tIRST
tIESU
tIEH
Table 5: Input-Only / Clock Cells
Parameter
Propagation Delays (ns)
Fanout
1 2 3 4 8 12 24
High Drive Input Delay
1.5 1.6 1.8 1.9 2.4 2.9 4.4
High Drive Input, Inverting Delay
1.6 1.7 .19 2.0 2.5 3.0 4.5
Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1 3.1
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
Input Register Clock To Q
0.7 0.8 1.0 1.1 1.6 2.1 3.6
Input Register Reset Delay
0.6 0.7 0.9 1.0 1.5 2.0 3.5
Input Register Clock Enable Setup Time
2.3 2.3 2.3 2.3 2.3 2.3 2.3
Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
Symbol
tACK
tGCKP
tGCKB
Table 6: Clock Cells
Parameter
Propagation Delays (ns)
Fanouta
1 2 3 4 8 10 11
Array Clock Delay
1.2 1.2 1.3 1.3 1.5 1.6 1.7
Global Clock Pin Delay
0.7 0.7 0.7 0.7 0.7 0.7 0.7
Global Clock Buffer Delay
0.8 0.8 0.9 0.9 1.1 1.2 1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks con-
sist of 44 half columns, each driven by an independent buffer. The number of half columns used
does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global
clock has up to 11 loads per half column.
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