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QL4090-2CF208C Ver la hoja de datos (PDF) - QuickLogic Corporation

Número de pieza
componentes Descripción
Fabricante
QL4090-2CF208C
QuickLogic
QuickLogic Corporation QuickLogic
QL4090-2CF208C Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
QL4009 QuickRAM Data Sheet Rev C
[8:0]
[17:0]
[1:0]
WA
RE
WD
WE
WCL K
MOD E
RCLK
[8:0]
RA
[17:0]
RD
ASYNCRD
Figure 4: QuickRAM Module
Symbol
tSWA
tHWA
tSWD
tHWD
tSWE
tHWE
tWCRD
Table 2: RAM Cell Synchronous Write Timing
Parameter
Propagation Delays (ns)
Fanout
1
2
3
4
5
WA Setup Time to WCLK
1.0 1.0 1.0 1.0 1.0
WA Hold Time to WCLK
0.0 0.0 0.0 0.0 0.0
WD Setup Time to WCLK
1.0 1.0 1.0 1.0 1.0
WD Hold Time to WCLK
0.0 0.0 0.0 0.0 0.0
WE Setup Time to WCLK
1.0 1.0 1.0 1.0 1.0
WE Hold Time to WCLK
WCLK to RD (WA=RA)a
0.0 0.0 0.0 0.0 0.0
5.0 5.3 5.6 5.9 7.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
Symbol
Logic Cells
tSRA
tHRA
tSRE
tHRE
tRCRD
Table 3: RAM Cell Synchronous Read Timing
Parameter
Propagation Delays (ns)
Fanout
1
2
3
4
5
RA Setup Time to RCLK
1.0 1.0 1.0 1.0 1.0
RA Hold Time to RCLK
0.0 0.0 0.0 0.0 0.0
RE Setup Time to RCLK
1.0 1.0 1.0 1.0 1.0
RE Hold Time to RCLK
0.0 0.0 0.0 0.0 0.0
RCLK to RDa
4.0 4.3 4.6 4.9 6.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
© 2003 QuickLogic Corporation
www.quicklogic.com •• 5

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