SDA9257 Ver la hoja de datos (PDF) - Siemens AG

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Fabricante

SDA9257

Clock Sync Generator

Siemens AG 

SDA 9257

HPLL Control (subaddress 01)

Relationship between Horizontal Frequency

in CVBS and Frequency on CKL1

1728

1716

1536

Control Bits

HPLL1

HPLL0

0

*)

1

0

1

1

Initiation of a Reset for HPLL

No function

HPLL is reset once, new lock-in process starts

Control Bit RSTH

0

1

Minimum Sync Pulse Length from which a Vertical Pulse is

Detected

26.6 µs

11.3 µs

Control Bit VTHRE

0

1

CVBS Clamping ON/OFF

Clamping ON

Clamping OFF

Control Bit CLOF

0

1

Selection of HPLL Lock-In Behavior

Optimum for VCR

Optimum for CVBS from network

Control Bit VCRTV

0

1

Freezing of the Actual Value of Clock Frequency

No function

Instantaneous increment is freezing so that the instantaneous

frequency value is frozen and there is no lock-in function

of HPLL

Control Bit FRZINC

0

1

Selection of Increment for Determining Clock Frequency

Increment from HPLL

Increment corresponding to I2C Bus bits INC00 … INC15

(frequency generator mode)

*) don’t care

Control Bit EXINC

0

1

Semiconductor Group

189

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