SCI7660C0B Ver la hoja de datos (PDF) - Seiko Epson Corp
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SCI7660C0B Datasheet PDF : 10 Pages
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SCI7660 Series
TYPICAL APPLICATIONS
Parallel Connection
Connecting two or more chips in parallel reduces the
output impedance by 1/n, where n is the number of de-
vices used.
VI = –5 V
VDD = 0 V
5V
1
2
1MΩ
3
4
8 + C2
7
10µF
6
C1
5 + 10µF
1
2
1MΩ
3
4
8
7
6
C1
5 + 10µF
VO = –10 V
Serial Connection
Connecting two or more chips in series obtains a higher
output voltage than can be obtained using a parallel
connection, however, this also raises the output imped-
ance.
VI = –5 V
VDD = 0 V
5V
1
2
1MΩ
3
4
8 + C2
7
10µF
6
C1
5 + 10µF
VDD' = VI = –5
1
2
1MΩ
3
4
VO = –10 V = VI'
8 + C2
7
10µF
6
C1
5 + 10µF
VO' = –15 V
Potential levels
VDD (0 V)
VI (–5 V)
VO (–10 V)
Primary stage
VDD
VI
VO (–15 V)
Secondary stage
1–8
EPSON
SCI7000 Series
Technical Manual
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