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SC2595 Datasheet PDF : 12 Pages
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SC2595
POWER MANAGEMENT
Application Information
Overview
Double Data Rate (DDR) SDRAM was defined by JEDEC
1997. Its clock speed is the same as previous SDRAM
but data transfers speed is twice than previous SDRAM.
By now, the requirement voltage range is changed from
3.3V to 2.5V; the power dissipation is smaller than
SDRAM. For above reasons, it is very popular and widely
used in M/B, N/B, Video-cards, CD ROM drives, Disk
drives.
PRELIMINARY
Application_2: Lower Power Loss Configuration
for SSTL-2
If power loss is a major concern, separated the PV form
CC
the AVCC and the VDDQ will be a good choice. The PVCC can
operate at lower voltage (1.8V to 2.5V). If 2.5V voltage
is applied on AV and the V , but the source current is
CC
DDQ
lower due to the lower operating voltage applied on the
PVCC. Please find the relative test result in Figures 5, 11
and 12.
Regarding the DDR power management solution, there
are two topologies can be selected for system design-
ers. One is switching mode regulator that has bigger sink/
source current capability, but the cost is higher and the
board space needed is bigger. Another solution is linear
mode regulator, which costs less, and needs the less
board space. For two DIMM motherboards, system de-
signers usually choose the linear mode for DDR power
management solution.
Applications
Typical Application Circuits & Waveforms
Two different application circuits are shown below in Fig-
ure 1 to Figure 2. Each circuit is designed for specific
condition. More details are described below. See Note
1. Below for recommended power up sequencing.
Application_1: Standard SSTL-2 Application
The AVCC pins, the PVCC pin, and the VDDQ pin can be tied
together for SSTL-2 application. It only needs a 2.5V
power rail for normal operation. System designer can
save the PCB space and reduce the cost. Please refer
to figures 3 to 4 for test waveforms.
SC2595
1 NC
VTT 8
2 GND
PVCC 7
3 VSENSE AVCC 6
4 VREF
VDDQ 5
Csence Cref
2.2uF 10nF
VDD
VTT
1.25V
2.5V
R1
5.1
Cin1
Cout1 Cout2
Cin2
1uF
68uF
220uF 10uF
SC2595
1
NC
VTT
2 GND
PVCC
3
VSENSE AVCC
4 VREF
VDDQ
Csense Cref
2.2uF 10nF
8
7
1.8V to 2.5V
6 2.5V VDD
Vin
5
R2 Cin2
R
1uF
Cin1
68uF
Cout1
220uF
VTT
1.25V
Cin2
10uF
Cddq
1uF
Figure 2: Lower power loss for SSTL-2 application
Notes:
(1) Power up of AVCC, PVCC and VDDQ supplies.
(a) The preferred mode of operation is when the
AV , PV and V pins are tied together to a
CC
CC
DDQ
single supply.
(b) If and when AVCC, PVCC pins are tied to a supply
separate to that of the V supply pin; then
DDQ
the V supply should lead AV , PV supply or
DDQ
CC
CC
the VDDQ supply and the AVCC, PVCC supply should
rise simultaneously.
(c) If the AV , PV and V supply pins are con
CC
CC
DDQ
nected in a way such that, AV , PV supplies
CC
CC
precedes VDDQ supply; then VTT output precedes
VDDQ. This can cause the SDRAM device to latch-
up, which may cause permanent damage to the
SDRAM.
Figure 1: Standard SSTL-2 application
©2009 Semtech Corp.
6
www.semtech.com
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