SC2595 Ver la hoja de datos (PDF) - Semtech Corporation

Número de pieza

componentes Descripción

Fabricante

SC2595

Integrated Linear DDR Termination Regulator

Semtech Corporation 

SC2595

POWER MANAGEMENT

Pin Descriptions

PRELIMINARY

SOIC-8L EDP Pin Name

Pin #

Pin Function

1

NC

No internal connection. (1)

2

GND

Ground.

3

VSENSE VSENSE is a feedback pin. VTT plane is always a narrow and long strip plane in most

motherboard applications. This long strip plane will cause a large trace

inductance and trace resistance. Consider the load transient condition; a fast

load current going through VTT strip plane can create voltage spikes on the VTT

plane. The load current can also cause a DC voltage drop on the VTT plane. It is

recommended that VSENSE should be connected to the center of VTT plane to

improve the load regulation and the noise immunity. In case that one can't

connect the VSENSE pin to the center of the VTT plane, one should connect it to the

SC2595 V pin directly. A longer trace of V may pick up noise and cause the

TT

SENSE

error of load regulation; hence the longer trace must be avoided.

A 10nF to 100nF ceramic capacitor close to the VSENSE pin is required to avoid

oscillation during transient condition.

4

VREF

VREF is an output pin, which provides the buffered output of the internal reference

voltage. System designer can use the VREF output voltage for Northbridge chipset

and memory. Because these input pins are typically high impedance, there

should be a small amount of current drawn from the VREF pin [figure 9, 10]. To

improve the noise immunity, a ceramic capacitor (10nF - 100nF) should be added

from the VREF pin to ground with short distance.

5

VDDQ(2) The VDDQ pin is an input for creating internal reference voltage to regulate VTT. The

VDDQ voltage is connected to internal 100Kohm resistor divider. The central tap

of resistor divider (VDDQ/2) is connected to the internal voltage buffer, which

output is connected to VREF pin and the non-inverting input of the error amplifier

as the reference voltage. With the feedback loop closed, the VTT output voltage

will always track the V /2 precisely. It is recommended to use 5.1 ohm + a

DDQ

1uF ceramic capacitor for VDDQ pin's filter to increase the noise immunity.

6

AVCC (2) The AVCC pin is used to supply all of the internal control circuitry. AVCC voltage

has to be greater than its UVLO threshold voltage (2.1V typical) to allow the

SC2595 be in normal operation. If AVCC voltage is lower than the UVLO threshold

voltage, the VTT output voltage will remain at 0V.

7

PVCC (2) The PVCC pin provides the rail voltage from where the VTT pin draws load current.

There is a limitation between AVCC and PVCC. The PVCC voltage must be less or

equal to AVCC voltage to ensure the correct output voltage regulation. The VTT

source current capability is dependent on PV voltage. Higher the voltage on

CC

PVCC, higher the source current; however, it will cause more power loss and higher

temperature rise [figure 5, 11, 12].

8

V TT

The VTT pin is the output of SC2595. It can sink and source 1.5A continuous

current and 3A peak current while keeping excellent load regulation. It is

recommended that one should use at least 220uF low ESR capacitors (ESR

should be lower than 250m ohm) and 10uF ceramic capacitors, which are

uniformly spread on the VTT strip plane to reduce the voltage spike under load

transient condition.

Thermal Thermal pad should be connected to GND.

Pad

©2009 Semtech Corp.

4

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