SAA7392 Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Fabricante
SAA7392 Datasheet PDF : 76 Pages
| |||
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.5 Bit recovery
The bit recovery block (shown in Fig.6) contains the slice
level circuitry, a noise filter to limit the HF-EFM signal noise
contribution, an adaptive slicer circuit and a digital PLL.
These blocks can be controlled via the microprocessor.
The channel rate should always obey the following
constraints:
• It should be less than 2 × the system clock
• It should be greater than 0.25 × the system clock.
In this clock range reliable bit clock detection is possible.
All data found will be written to the FIFO. It is the
responsibility of the user to select BCLK and system clock
values so that the FIFO operation is controlled.
The digital noise filter runs on the PLL bit clock and limits
the bandwidth of the incoming signal to 0.25 of the PLL bit
clock frequency. The characteristics of the filter are:
• Passband: 0 to 0.22 fb
• Stopband: 0.28 fb to (fclk − 0.28 fb)
• Rejection: −28 dB.
The slice level determination circuit compensates the
incoming signal asymmetry component. The bandwidth of
this circuit is programmable via register PLLSet.
A programmable (one tap presetable, asymmetrical)
equaliser is used in the bit detection circuit. The first and
last tap settings are different. Possible tap values are
settable via register PLLEqu.
The advanced detector has two extra detection circuits
(adaptive slicer and run length 2 push-back) which are
controlled via the VitSet register, that allow improved
margin in the bit detector.
The adaptive slicer does a second stage slice operation;
the bandwidth is higher than the first slicer. It can be turned
on/off via the VitSet register.
If the advanced detector is switched on all run length 2
symbols are pushed back to run length 3. The circuit will
determine the transition that was most likely to be in error,
and shift the transition on that edge.
handbook, fGulAl pIaNgeCwOidNthTROLLED
AMPLIFIER
HIN
ADC
GAIN CONTROL
BLOCK
++
−
NOISE
FILTER
DIGITAL
EQUALIZER
SLICE LEVEL
DETERMINE
clocked on PLL clock
VITERBI
DETECTOR
ZERO TRANS
DETECTOR
DIGITAL
PLL
RMS JITTER
MEASUREMENT
MULTIPLEXER
jitter value
PLL frequency
slice level
MEAS1
MGR796
2000 Mar 21
Fig.6 Block diagram of bit recovery block.
19
Share Link: 