Philips Semiconductors
High performance Compact
Disc-Recordable (CD-R) controller
Preliminary specification
SAA7390
The SAA7390 comprises four major functional blocks:
• The front-end block connects to the external CD-60
based decoder and fully processes the incoming data
stream
• The buffer manager block provides the address
generation and timing control for the external DRAMs
• The ECC block performs the error correction functions in
hardware on the data stored in the DRAM buffer.
• The block encoder function (realized via a modified
CDB2) serializes the data from the buffer, appends the
sync pattern, header, sub-header, third level ECC parity
and EDC bytes as necessary, performs the required
scrambling and outputs them to the CDCEP using a
special data clock (98 clock cycles per word selection
period).
3 QUICK REFERENCE DATA
SYMBOL
VDD
Tamb
Tstg
PARAMETER
digital supply voltage
operating ambient temperature
storage temperature
MIN.
4.5
0
−55
TYP.
5.0
−
−
MAX.
5.5
70
+150
UNIT
V
°C
°C
4 ORDERING INFORMATION
TYPE
NUMBER
SAA7390GP(1)
PACKAGE
NAME
DESCRIPTION
SQFP128 plastic quad flat package; 128 leads (lead length 1.6 mm);
body 14 × 20 × 2.8 mm
Note
1. This device uses a Symbios logic package.
VERSION
SOT387-2
1996 Jul 02
4