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SAA7325

Digital servo processor and Compact Disc decoder with integrated DAC (CD10)

Philips Electronics 

Philips Semiconductors

Digital servo processor and Compact Disc

decoder with integrated DAC (CD10)

Product specification

SAA7325

7.1.3 LOCK-TO-DISC MODE

Although nominally a single-speed device, for electronic

shock absorption applications the SAA7325 can be put

into lock-to-disc mode. This allows Constant Angular

Velocity (CAV) disc playback with varying input data rates

from the inside-to-outside of the disc. In the lock-to-disc

mode, the FIFO is blocked and the decoder will adjust its

output data rate to the disc speed. Hence, the frequency of

the I2S-bus (WCLK and SCLK) clocks are dependent on

the disc speed. In the lock-to-disc mode there is a limit on

the maximum variation in disc speed that the SAA7325 will

follow. Disc speeds must always be within 25% to 100%

range of their nominal value. The lock-to-disc mode is

enabled/disabled by decoder register E.

7.1.4 STANDBY MODES

The SAA7325 may be placed in two standby modes

selected by decoder register B (it should be noted that the

device core is still active):

• Standby 1: ‘CD-STOP’ mode; most I/O functions are

switched off

• Standby 2: ‘CD-PAUSE’ mode; audio output features

are switched off, but the motor loop, the motor output

and the subcode interfaces remain active; this is also

called a ‘Hot Pause’.

In the standby modes the various pins will have the

following values:

• MOTO1 and MOTO2: put in high-impedance, PWM

mode (standby 1 and reset: operating in standby 2); put

in high-impedance, PDM mode (standby 1 and reset:

operating in standby 2)

• SCL and SDA: no interaction; normal operation

continues

• SCLK, WCLK, DATA, EF and DOBM: 3-state in both

standby modes; normal operation continues after reset

• CRIN, CROUT, CL16 and CL11/4: no interaction;

normal operation continues

• V1, V2/V3, V4, V5 and CFLG: no interaction; normal

operation continues.

Table 1 Operating frequencies

REGISTER B(1)

00XX

00XX

01XX

01XX

SELPLL

0

1

0

1

CRYSTAL FREQUENCY (MHz)

33.8688

√

−

−

−

16.9344

−

−

√

√

8.4672

−

√

−

−

CL11 FREQUENCY (MHz)(2)

11.2896

11.2896

5.6448

11.2896

Notes

1. The MSB of register B must be held at 0 (i.e. 0XXX).

2. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. CL11 is

available on the CL11/4 output, enabled by programming shadow register 3 (see Section 7.15.3).

1999 Jun 17

9

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