SAA7325 Ver la hoja de datos (PDF) - Philips Electronics

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SAA7325

Digital servo processor and Compact Disc decoder with integrated DAC (CD10)

Philips Electronics 

Philips Semiconductors

Digital servo processor and Compact Disc

decoder with integrated DAC (CD10)

Product specification

SAA7325

100 nF

VSSA

HF input

1 nF

47 pF

2.2 kΩ

HFREF

HFIN

22 kΩ

100 nF

VSSA

ISLICE

crystal

clock

DQ

100 µA

100 µA

VSS

VDD

DPLL

MGS179

Fig.6 Data slicer showing typical application components.

7.4 Demodulator

7.4.1 FRAME SYNC PROTECTION

A double timing system is used to protect the demodulator

from erroneous sync patterns in the serial data.

The master counter is only reset if:

• A sync coincidence is detected; sync pattern occurs

588 ±1 EFM clocks after the previous sync pattern

• A new sync pattern is detected within ±6 EFM clocks of

its expected position.

The sync coincidence signal is also used to generate the

PLL lock signal, which is active HIGH after 1 sync

coincidence found, and reset LOW if during 61

consecutive frames no sync coincidence is found. The PLL

lock signal can be accessed via the SDA or STATUS pins

selected by decoder registers 2 and 7.

Also incorporated in the demodulator is a Run Length 2

(RL2) correction circuit. Every symbol detected as RL2 will

be pushed back to RL3. To do this, the phase error of both

edges of the RL2 symbol are compared and the correction

is executed at the side with the highest error probability.

7.4.2 EFM DEMODULATION

The 14-bit EFM data and subcode words are decoded into

8-bit symbols.

1999 Jun 17

11

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