SAA7325 Ver la hoja de datos (PDF) - Philips Electronics

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SAA7325

Digital servo processor and Compact Disc decoder with integrated DAC (CD10)

Philips Electronics 

Philips Semiconductors

Digital servo processor and Compact Disc

decoder with integrated DAC (CD10)

Product specification

SAA7325

7.2 Crystal oscillator

The crystal oscillator is a conventional 2-pin design

operating between 8 and 35 MHz. This oscillator is

capable of operating with ceramic resonators and with

both fundamental and third overtone crystals. External

components should be used to suppress the fundamental

output of the third overtone crystals as shown in

Figs 3 and 4. Typical oscillation frequencies required are

8.4672, 16.9344 or 33.8688 MHz depending on the

internal clock settings used and whether or not the clock

multiplier is enabled (see Table 1).

handbook, halfpagSe AA7325

OSCILLATOR

CROUT

8.4672 MHz

CRIN

33 pF

33 pF

7.3 Data slicer and clock regenerator

The SAA7325 has an integrated slice level comparator

which can be clocked by the crystal frequency clock, or

4 times the crystal frequency clock (if SELPLL is set HIGH

while using a 16.9344 MHz crystal and register 4 is set

to 0XXX), or 8 times the crystal frequency clock

(if SELPLL is set HIGH while using an 8.4672 MHz crystal,

and register 4 is set to 0XXX). The slice level is controlled

by an internal current source applied to an external

capacitor under the control of the Digital Phase-Locked

Loop (DPLL).

Regeneration of the bit clock is achieved with an internal

fully digital PLL. No external components are required and

the bit clock is not output. The PLL has two registers

(8 and 9) for selecting bandwidth and equalization.

The PLL response is shown in Fig.5.

For certain applications an off-track input is necessary.

This is internally connected from the servo part (its polarity

can be changed by the foc_parm1 parameter), but may be

input via the V1 pin if selected by register C. If this flag is

HIGH, the SAA7325 will assume that its servo part is

following on the wrong track, and will flag all incoming HF

data as incorrect.

MGL694

Fig.3 8.4672 MHz fundamental configuration.

handbook, halfpage

PLL

loop

response

handbook, halfpagSe AA7325

OSCILLATOR

CROUT

33.8688 MHz

CRIN

3.3 µH

MGL695

10 pF

10 pF

1 nF

3. PLL, LPF

2. PLL bandwidth

1. PLL integrator

f

MGS178

1, 2 and 3 are all programmable via decoder register 8.

Fig.5 Digital PLL loop response.

Fig.4 33.8688 MHz overtone configuration.

1999 Jun 17

10

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