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SA8028

2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers

Philips Electronics 

Philips Semiconductors

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

Product data

SA8028

1.5 RF and IF Charge Pumps

The RF phase detector drives the charge pumps on the PHP and

PHI pins, while the IF phase detector drives the charge pump on the

PHA pin. Both the RF and IF charge pump current values are

determined by the current generated at the RSET pin1. The current

gain can be further programmed by the CP0, CP1 bits in the C-word,

as seen in Table 1.

Table 1. RF and IF charge pump currents

CP1 2 CP0

0

0

0

1

1

0

1

1

IPHA

1.5xlSET

0.5xlSET

1.5xlSET

0.5xlSET

IPHP

3xISET

1xlSET

3xlSET

1xlSET

IPHP–SU 3

15xlSET

5xlSET

15xlSET

5xlSET

IPHI

36xlSET

12xlSET

0

0

NOTES

1. ISET = VSET/RSET: bias current for charge pumps.

2. CP1 = 1 is used to disable the PHI pump.

3. IPHP–SU is the total current at pin PHP during speed up condition.

1.6 Charge Pumps Speed-up Mode

The RF charge pumps will enter speed-up mode when STROBE

goes high after A-word has been sent. They will exit speed-up mode

on the next falling edge of STROBE. There is no speed-up mode for

the IF charge pump.

The charge pump, by default, will automatically go into speed-up

mode (which can deliver up to 15*ISET for PHP_SU, and 36*ISET for

PHI), based on the strobe pulse width following the A-word to

reduce switching speed for large tuning voltage steps (i.e., large

frequency steps). Figure 7 shows the recommended passive loop

filter configuration. Note: This charge pump architecture eliminates

the need for added active switches and reduces external component

count. Furthermore, the programmable charge pump gains provide

some programmability to the loop filter bandwidth.

The duration of speed-up mode is determined by the strobe pulse

that follows the A-word. Recommended optimal strobe width is equal

to the total loop filter capacitance charge time from VCO control

voltage level 1 to VCO control voltage level 2. The strobe width must

not exceed this charge time. An external data processing unit

controls the width of the strobe pulse (e.g., × number of clock

cycles).

In addition, charge pumps will stay in speed-up mode continuously

while Tspu = 1 (in D-word <D15>). The speed-up mode can also be

disabled by programming Tdis-spu = 1 (in D-word <D16>).

PHP[PHP–SU]

PHI

R2

R1

C2

C1

VCO

C3

1.7 Lock Detect

The output LOCK maintains a logic ‘1’ when the IF phase detector

(AND/ORed) with the RF phase detector indicates a lock condition.

The lock condition for the RF and IF synthesizers is defined as a

phase difference of less than "1 period of the frequency at the input

REFin+, REFin–. One counter can fulfill the lock condition when the

other counter is powered down. Out of lock (logic ‘0’) is indicated

when both counters are powered down.

1.8 Power-down mode

With power applied to the chip, power-down mode can be entered

either by hardware (external signal on pin PON) or by software (by

programming the PD = Power Down bits (<B10, B9>) in the B-word).

The PON signal is exclusively ORed with the PD bits. If PON = 0,

then the part is powered up when PD = 1 (<B10, B9>). PON can be

used to invert the polarity of the software bits PD. Table 9 of section

2.4.2 illustrates how power-down mode can be implemented.

During power-down mode the 3-wire bus remains active and

programming-words may be pre-loaded before switching to

power-up mode. If the chip is programmed while in power-down

mode, the RF divider ratio NRF is internally presented to the RF

divider on the next falling edge of STROBE after STROBE has gone

high at the end of the A-word. Power-down mode does not reset the

sigma-delta modulator., i.e., power-down mode preserves the state

of the sigma-delta modulator (as long as power is applied to the

chip).

To take advantage of the register pre-loading capability while the

device is in power-down mode, the B-word needs to be sent a

second time (i.e., again, after the A-word), with the PD (<B10, B9>)

bits now programmed for power-up.

If power-up mode is to be controlled by hardware, the PON signal

must be toggled only after the A-word has been sent and STROBE

has gone high and then low.

When the synthesizer is reactivated after power-down mode, the IF

and reference dividers are synchronized to avoid random phase

errors on power-up. There is no power-up synchronization between

the RF divider and the reference clock. After power-up, there is a

delay of four edges (i.e. 1.5 cycles) of the output clock of the

reference divider before the RF phase detector is activated. That

means the reference divider must be powered up for the RF phase

detector to become active.

When initially applying or reapplying power to the chip, and internal

power-up reset pulse is generated which sets the programming-words

to their default values and also resets the sigma-delta modulator to

its “all-0” state. It is also recommended that the D-word be manually

reset to all zeros, following initial power-up, to avoid unknown states.

SR02356

Figure 7. Typical passive 3-pole loop filter.

2002 Feb 22

10

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