S3C72P9 Ver la hoja de datos (PDF) - Samsung

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componentes Descripción

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S3C72P9

The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrange

Samsung 

S3C72P9/P72P9 (Preliminary Spec)

BLOCK DIAGRAM

PRODUCT OVERVIEW

P1.0-P1.3/

INT0-INT4

P2.0/CLO

P2.1/LCDCK

P2.2/LCDSY

P3.0/TCLO0

P3.1/TCLO1

P3.2/TCL0

P3.3/TCL1

P4.0-P4.3/

COM8-COM11

P5.0-P5.3/

COM12-COM15

P6.0-P6.3/

SEG55-SEG52/

K4-K7

P7.0-P7.3/

SEG51-SEG48

P8.0-P8.3/

SEG47-SEG44

P9.0-P9.3/

SEG43-SEG40

Input Port 1

I/O Port 2

I/O Port 3

I/O Port 4

I/O Port 5

I/O Port 6

I/O Port 7

I/O Port 8

I/O Port 9

RESET

XIN XOUT

XTIN XTOUT

Interrupt

Control

Block

Clock

Instruction

Register

Internal

Interrupts

Instruction Decoder

Arithmetic

and

Logic Unit

Program

Counter

Program

Status Word

Stack

Pointer

1,056 x 4-Bit

Data

Memory

32,768 x 8-Bit

Program

Memory

Watchdog

Timer

Basic Timer

Watch Timer

LCD

Driver/

Controller

LCD Contrast

Controller

SIO

I/O Port 0

8-Bit Timer/

Counter

16-Bit Timer/

Counter

VLC1-VLC5

COM0-COM7

P4.0-P4.3/

CO8-COM11

P5.0-P5.3/

COM12-COM15

SEG0-SEG39

P9.3-P6.0/

SEG40-SEG55

P0.0/SCK/K0

P0.1/SO/K1

P0.2/SI/K2

P0.3/BUZ/K3

Figure 1-1. S3C72P9/P72P9 Simplified Block Diagram

1–3

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