S3C72N4 Ver la hoja de datos (PDF) - Samsung

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S3C72N4

The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47

Samsung 

ELECTRICAL DATA

TIMING WAVEFORMS

S3C72N2/C72N4/P72N4

VDD

RESET

EXECUTION OF

STOP INSTRUCTION

STOP MODE

DATA RETENTION MODE

INTERNAL RESET

OPERATION

IDLE MODE

OPERATING

MODE

VDDDR

tSREL

tWAIT

Figure 13-2. Stop Mode Release Timing When Initiated By RESET

VDD

EXECUTION OF

STOP INSTRUCTION

STOP MODE

DATA RETENTION MODE

VDDDR

POWER-DOWN MODE TERMINATING SIGNAL

(INTERRUPT REQUEST)

IDLE MODE

NORMAL

OPERATING

MODE

tSREL

tWAIT

Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request

13-10

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