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S3C72I9

The S3C72I9 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47

Samsung 

PRODUCT OVERVIEW

S3C72I9/P72I9

Table 1-1. S3C72I9 Pin Descriptions (Continued)

Pin Name

INT2

INT4

CLO

LCDCK

LCDSY

TCLO0

TCLO1

TCL0

TCL1

COM0-COM7

COM8-COM11

COM12-COM15

SEG0-SEG39

SEG40-SEG43

SEG44-SEG47

SEG48-SEG51

SEG52-SEG55

K0-K3

K4-K7

VDD

VSS

RESET

VLC1-VLC5

Xin, Xout

XTin, XTout

TEST

Pin Type

I

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

I/O

Description

Quasi-interrupt with detection of rising or

falling edges.

External interrupt with detection of rising or

falling edges.

Clock output .

LCD clock output for display expansion.

LCD synchronization clock output for display

expansion.

Timer/counter 0 clock output.

Timer/counter 1 clock output.

External clock input for timer/counter 0.

External clock input for timer/counter 1.

LCD common signal output.

O

LCD segment signal output.

I/O

I/O

External interrupt. The triggering edge is

selectable.

–

Main power supply.

–

Ground.

I

Reset signal.

–

LCD power supply.

–

Crystal, Ceramic or RC oscillator pins for

system clock.

–

Crystal oscillator pins for subsystem clock.

I

Test signal input. (must be connected to VSS)

Number

25

26

27

28

29

30

31

32

33

34-41

42-45

46-49

5-1,

100-66

65-62

61-58

57-54

53-50

11-14

50-53

15

16

22

10-6

18, 17

20, 21

19

Share Pin

P1.2

P1.3

P2.0

P2.1

P2.2

P3.0

P3.1

P3.2

P3.3

–

P4.0-P4.3

P5.0-P5.3

–

P9.3-P9.0

P8.3-P8.0

P7.3-P7.0

P6.3/K7-P6.0/K4

P0.0-P0.3

P6.0-P6.3

–

–

–

–

–

–

–

NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

1-6

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