S29GL256P90TAC012 Ver la hoja de datos (PDF) - Spansion Inc.

Número de pieza

componentes Descripción

Fabricante

S29GL256P90TAC012

S29GL-P MirrorBit® Flash Family

Spansion Inc. 

Data Sheet

2. Input/Output Descriptions & Logic Symbol

Table 2.1 identifies the input and output package connections provided on the device.

Table 2.1 Input/Output Descriptions

Symbol

A25–A0

DQ14–DQ0

DQ15/A-1

CE#

OE#

WE#

VCC

VIO

VSS

NC

RY/BY#

BYTE#

RESET#

WP#/ACC

Type

Input

I/O

I/O

Input

Input

Input

Supply

Supply

Supply

No Connect

Output

Input

Input

Input

Description

Address lines for GL01GP

A24–A0 for GL512P

A23–A0 for GL256P,

A22–A0 for GL128P.

Data input/output.

DQ15: Data input/output in word mode.

A-1: LSB address input in byte mode.

Chip Enable.

Output Enable.

Write Enable.

Device Power Supply.

Versatile IO Input.

Ground.

Not connected internally.

Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At

VIL, the device is actively erasing or programming. At High Z, the device is in ready.

Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-

DQ7 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in

word configuration and data I/O pins DQ0-DQ15 are active.

Hardware Reset. Low = device resets and returns to reading array data.

Write Protect/Acceleration Input. At VIL, disables program and erase functions in the

outermost sectors. At VHH, accelerates programming; automatically places device in

unlock bypass mode. Should be at VIH for all other conditions. WP# has an internal pull-

up; when unconnected, WP# is at VIH.

October 22, 2012 S29GL-P_00_A14

S29GL-P MirrorBit® Flash Family

11

Share Link: