S2100R Ver la hoja de datos (PDF) - Seiko Instruments Inc

Número de pieza

componentes Descripción

Fabricante

S2100R

64-bit FUSE ROM

Seiko Instruments Inc 

64-bit FUSE ROM

S-2100R

Read Mode Operation

By setting the CE/PE terminal to “ L” level, the S-2100R enters the read mode. *1 Next, adding an RST pulse causes the

contents of the memory bit of address 1 to be output at the DATA terminal; the rising of the RST pulse latches the data and

stabilizes it. *2 Reading of addresses from 2 to 64 can be done by adding a CLK pulse sequentially after reading address 1. *3

As soon as address 64 has been read, the COUNTER OUT terminal outputs “ H” level. When it finishes reading address 64, it

does not accept any more CLK pulses and the counter does not operate. The data of address 64 is maintained till address 1 is

read by the RST pulse.

CE/PE

RST

CLK

DATA

tCES

tCE

tRH

tRC

tACC

Address 1 output

tCH

tRC

tACC

Address 2 output

tRC

Address 3 output

Figure 3 Read mode timing

tRS

Address 1 output

*1 When both the CLK and RST terminals are at “ H” level.

*2 When the RST terminal is at “ L” level, the latch is transparent and the data is recognized by the rising of the RST pulse.

*3 Data read by the CLK pulse is latched at its rising.

Counter Hold Mode Operation

By setting the CE/PE terminal to “ H” level, the S-2100R enters the counter hold mode and the DATA terminal becomes high

impedance.

*4

In counter hold mode, the CLK and RST pulses which fall while the CE/PE terminal is at “ H” level are recognized to be invalid

and there is no change in counter and data output. When the CE/PE terminal is set to “ L” level again, it returns to the

condition in which it was before the counter hold mode.

CE/PE

tCRI

RST

CLK

DATA

Address M

output

tCES

tCS

tWZ

Address M+1 output

Figure 4 Counter hold mode timing

Address M+1 output

*4 When both the CLK and RST terminals are at “ H” level.

4

Seiko Instruments Inc.

Share Link: