RT9703 Ver la hoja de datos (PDF) - Richtek Technology
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RT9703 Datasheet PDF : 14 Pages
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Applications Information
The RT9703 is a high-side, N-Channel, power switch
available with active-high enable input. Low RDS(ON)d≈d
80mΩ and full protection functions make it optimized to
replace complex discrete on/off control circuitry.
Input and Output
VIN (input) is the power source connection to the internal
circuitry and the drain of the MOSFET. VOUT (output) is
the source of the MOSFET. In a typical application, current
flows through the switch from VIN to VOUT toward the load.
If VOUT is greater than VIN, current will flow from VOUT to
VIN since the MOSFET is bidirectional when on.
Unlike a normal MOSFET, there is no a parasitic body
diode between drain and source of the MOSFET, the
RT9703 prevents reverse current flow if VOUT being
externally forced to a higher voltage than VIN when the
output disabled (VEN < 0.8V).
D
SD
S
G
Normal MOSFET
G
RT9703
Chip Enable Input
The switch will be disabled when the EN pin is in a logic
low condition. During this condition, the internal circuitry
and MOSFET are turned off, reducing the supply current
to 0.1μA typically. The maximum guaranteed voltage for a
logic low at the EN pin is 0.8V. A minimum guaranteed
voltage of 2V at the EN pin will turn the RT9703 back on.
Floating the input may cause unpredictable operation. EN
should not be allowed to go negative with respect to GND.
The EN pin may be directly tied to VIN to keep the part on.
Soft-Start for Hot Plug-In Applications
In order to eliminate the upstream voltage droop caused
by the large inrush current during hot-plug events, the
“soft-start” feature effectively isolates the power source
from extremely large capacitive loads.
RT9703
Fault Flag
The RT9703 provides a FLG signal pin which is an
N-Channel open drain MOSFET output. This open drain
output goes low when VOUT < VIN −1V, current limit or the
die temperature exceeds 130°C approximately. The FLG
output is capable of sinking a 10mA load to typically
150mV above ground. The FLG pin requires a pull-up
resistor, this resistor should be large in value to reduce
energy drain. A 100kΩ pull-up resistor works well for most
applications. In the case of an over-current condition, FLG
will be asserted only after the flag response delay time,
tD, has elapsed. This ensures that FLG is asserted only
upon valid over-current conditions and that erroneous
error reporting is eliminated.
For example, false over-current conditions may occur
during hot-plug events when a highly large capacitive load
is connected and causes a high transient inrush current
that exceeds the current limit threshold. The FLG
response delay time tD is typically 4.6ms.
Under-voltage Lockout
Under-voltage lockout (UVLO) prevents the MOSFET switch
from turning on until input voltage exceeds approximately
1.7V. If input voltage drops below approximately 1.3V, UVLO
turns off the MOSFET switch, FLG will be asserted
accordingly. Under- voltage detection functions only when
the chip enable input is enabled.
Current Limiting and Short-Circuit Protection
The current limit circuitry prevents damage to the MOSFET
switch and external load. It is user adjust- able with an
external set resistor, RSET, ILIMIT = 210kΩ/RSET in the range
of 0.5A to 3A. The accuracy of current limit set point may
vary with operating temperature and supply voltage. See
“Typical Operating Characteristics” graph for further details.
DS9703-08 March 2007
www.richtek.com
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