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RT9173C Ver la hoja de datos (PDF) - Richtek Technology

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RT9173C Datasheet PDF : 13 Pages
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RT9173C
Typical Application Circuit
VCNTL = 3.3V
VIN = 2.5V/1.8V/1.5V
2N7002
EN
RTT
R1
VIN
VCNTL
CIN CCNTL
RT9173C
REFEN
VOUT
R2
CSS
GND
COUT
GND
R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω
COUT(MIN) = 10μF (Ceramic) + 1000μF under the worst case testing condition
CSS = 1μF, CIN = 470μF (Low ESR), CCNTL = 47μF
Functional Pin Description
VIN (Pin 1)
Input voltage which supplies current to the output pin. Connect this pin to a well-decoupled supply voltage. To prevent the
input rail from dropping during large load transient, a large, low ESR capacitor is recommended to use. The capacitor
should be placed as close as possible to the VIN pin.
GND [Pin 2, Exposed pad (9)]
Common Ground (Exposed pad is connected to GND). The GND pad area should be as large as possible and using many
vias to conduct the heat into the buried GND plate of PCB layer.
VCNTL (Pin 6)
VCNTL supplies the internal control circuitry and provides the drive voltage. The driving capability of output current is
proportioned to the VCNTL. Connect this pin to 3.3V bias supply to handle large output current with at least 10μF
capacitor from this pin to GND.
REFEN (Pin 3)
Reference voltage input and active low shutdown control pin. Two resistors dividing down the VIN voltage on the pin to
create the regulated output voltage. Pulling the pin to ground turns off the device by an open-drain, such as 2N7002,
signal N-Channel MOSFET.
VOUT (Pin 4)
Regulator output. VOUT is regulated to REFEN voltage that is used to terminate the bus resistors. It is capable of sinking
and sourcing current while regulating the output rail. To maintain adequate large signal transient response, typical value
of 1000μF AL electrolytic capacitor with 10μF ceramic capacitors are recommended to reduce the effects of current
transients on VOUT.
NC (Pin 5, 7, 8)
No Internal Connect.
www.richtek.com
2
DS9173C-12 September 2007

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