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LH28F800SU

8M (512K × 16, 1M × 8) Flash Memory

Sharp Electronics 

LH28F800SU

8M (512K × 16, 1M × 8) Flash Memory

56-PIN TSOP

TOP VIEW

3/5 1

CE1

2

NC 3

NC 4

A19

5

A18

6

A17

7

A16

8

VCC

9

A15 10

A14 11

A13 12

A12 13

CE0 14

VPP 15

RP 16

A11 17

A10 18

A9 19

A8 20

GND 21

A7 22

A6 23

A5 24

A4 25

A3 26

A2 27

A1 28

56 WP

55 WE

54 OE

53 RY/BY

52 DQ15

51 DQ7

50 DQ14

49 DQ6

48 GND

47 DQ13

46 DQ5

45 DQ12

44 DQ4

43 VCC

42 GND

41 DQ11

40 DQ3

39 DQ10

38 DQ2

37 VCC

36 DQ9

35 DQ1

34 DQ8

33 DQ0

32 A0

31 BYTE

30 NC

29 NC

28F800SUR-17

Figure 2. TSOP Configuration

INTRODUCTION

Sharp’s LH28F800SU 8M Flash Memory is a revolu-

tionary architecture which enables the design of truly

mobile, high performance, personal computing and com-

munication products. With innovative capabilities, 5 V

single voltage operation and very high read/write per-

formance, the LH28F800SU is also the ideal choice for

designing embedded mass storage flash memory sys-

tems.

The LH28F800SU is a very high density, highest per-

formance non-volatile read/write solution for solid-state

storage applications. Its symmetrically blocked archi-

tecture (100% compatible with the LH28F008SA 8M

Flash memory, the LH28F016SA 16M Flash memory

and the LH28F016SU 16M 5 V single voltage Flash

memory), extended cycling, low power 3.3V operation,

very fast write and read performance and selective block

locking provide a highly flexible memory component suit-

able for high density memory cards, Resident Flash

Arrays and PCMCIA-ATA Flash Drives. The

LH28F800SU’s dual read voltage enables the design of

memory cards which can interchangeably be read/writ-

ten in 3.3 V and 5.0 V systems. Its x8/x16 architecture

allows the optimization of memory to processor inter-

face. The flexible block locking option enables bundling

of executable application software in a Resident Flash

Array or memory card. Manufactured on Sharp’s 0.55

µm ETOX™ process technology, the LH28F800SU is

the most cost-effective, high-density 3.3V flash memory.

DESCRIPTION

The LH28F800SU is a high performance 8M

(8,388,608 bit) block erasable non-volatile random

access memory organized as either 512K × 16 or

1M × 8.The LH28F800SU includes sixteen 64K (65,536)

blocks or sixteen 32-KW (32,768) blocks. A chip memory

map is shown in Figure 3.

The implementation of a new architecture, with many

enhanced features, will improve the device operating

characteristics and results in greater product reliability

and ease of use.

Among the significant enhancements of the

LH28F800SU:

• 5 V Write/Erase Operation (5 V VPP)

• 3.3 V Low Power Capability (2.7 V VCC Read)

• Improved Write Performance

• Dedicated Block Write/Erase Protection

A 3/5 » input pin reconfigures the device internally for

optimized 3.3 V or 5.0 V read/write operation.

2

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