RT8062GSP Ver la hoja de datos (PDF) - Richtek Technology
Número de pieza
componentes Descripción
Fabricante
RT8062GSP Datasheet PDF : 11 Pages
| |||
RT8062
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. Highest efficiency operation is achieved by reducing
ripple current at low frequency, but it requires a large
inductor to attain this goal.
For the ripple current selection, the value of ΔIL = 0.4(IMAX)
will be a reasonable starting point. The largest ripple current
occurs at the highest VIN. To guarantee that the ripple
current stays below a specified maximum, the inductor
value should be chosen according to the following
equation :
⎡
L= ⎢
VOUT
⎤⎡
⎥ ⎢1−
VOUT
⎤
⎥
⎢⎣ f × ΔIL(MAX) ⎥⎦ ⎢⎣ VIN(MAX) ⎥⎦
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant
frequency architectures by preventing sub harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by adding a compensating ramp
to the inductor current signal. Normally, the maximum
inductor peak current is reduced when slope compensation
is added. In IC, however, separated inductor current signal
is used to monitor over current condition and this keeps
the maximum output current relatively constant regardless
of duty cycle.
Hiccup Mode Under Voltage Protection
A Hiccup Mode Under Voltage Protection (UVP) function
is provided for the IC. When the FB voltage drops below
half of the feedback reference voltage, VFB, the UVP
function will be triggered to auto re-softstart the power
stage until this event is cleared. The Hiccup Mode UVP
can reduce input current in short circuit conditions, and
not be triggered during softstart process.
Under Voltage Lockout Threshold
The IC exists an input under voltage lockout protection
(UVLO). If the input voltage exceeds the UVLO rising
threshold voltage, the converter will reset and prepare the
PWM for operation. If the input voltage falls below the
UVLO falling threshold voltage during normal operation,
the device will stop switching. The UVLO rising and falling
threshold voltage exist a hysteresis to prevent noise
caused reset.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θJA, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. The maximum power dissipation at TA
= 25°C can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
for SOP-8 (Exposed Pad) package
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
DS8062-07 November 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
Share Link: 