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RT8061A Ver la hoja de datos (PDF) - Richtek Technology

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RT8061A Datasheet PDF : 12 Pages
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RT8061A
Typical Application Circuit
PGOOD
RT8061A
4 PGOOD LX 2, 3
LOUT
R1
VIN
9, 10 PVIN
CIN
8 SVIN
FB 6
C1
RFB1 CFF
RFB2
Chip Enable
5 EN
GND 11 (Exposed Pad)
VOUT
COUT
Functional Pin Description
Pin No.
Pin Name
Pin Function
1, 7
NC
No Internal Connection.
2, 3
LX
Switch Node. Connection this pin to the inductor.
4
PGOOD
Power Good Indicator. This pin is an open drain logic output that is pulled to
ground when the output voltage is less than 90% of the target output voltage.
5
EN
Enable Control. Pull high to turn on. Do not float.
6
FB
Feedback. This pin receives the feedback voltage from a resistive voltage divider
connected across the output.
8
SVIN
Signal Input. Decouple this pin to GND with at least 1μF ceramic cap.
9, 10
PVIN
11 (Exposed Pad) GND
Power Input. Decouple this pin to GND with at least 4.7μF ceramic cap.
The exposed pad must be soldered to a large PCB and connected to GND for
maximum power dissipation.
Function Block Diagram
EN
PGOOD
EN
PGOOD
OSC
Slope
Com
ISEN
PVIN
0.6V
EN
FB
Output
Clamp
OC
Limit
Int-SS
Driver
LX
0.72V
OV
Control
0.54V
Logic
POR
0.4V
PGOOD
UV
VREF
OTP
NISEN
Zero Current
SVIN
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
is a registered trademark of Richtek Technology Corporation.
DS8061A-04 September 2012

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