H1130I Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Fabricante
H1130I Datasheet PDF : 12 Pages
| |||
HFA1130
Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
PARAMETER
(NOTE 2)
TEST
TEST TEMP.
CONDITIONS
LEVEL (°C)
MIN
TYP
MAX
UNITS
Negative Clamp Range
B
25
-
-5.0 to +2.0
-
V
Positive Clamp Range
B
25
-
-2.0 to +5.0
-
V
Clamp Input Bias Current
A
25
-
50
200
µA
Clamp Input Bandwidth
VH or VL = 100mVP-P
B
25
-
500
-
MHz
NOTES:
2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
3. See Typical Performance Curves for more information.
Application Information
Optimum Feedback Resistor (RF)
The enclosed plots of inverting and non-inverting frequency
response detail the performance of the HFA1130 in various
gains. Although the bandwidth dependency on ACL isn’t as
severe as that of a voltage feedback amplifier, there is an
appreciable decrease in bandwidth at higher gains. This
decrease can be minimized by taking advantage of the current
feedback amplifier’s unique relationship between bandwidth
and RF. All current feedback amplifiers require a feedback
resistor, even for unity gain applications, and the RF, in
conjunction with the internal compensation capacitor, sets the
dominant pole of the frequency response. Thus, the
amplifier’s bandwidth is inversely proportional to RF. The
HFA1130 design is optimized for a 510Ω RF, at a gain of +1.
Decreasing RF in a unity gain application decreases stability,
resulting in excessive peaking and overshoot (Note:
Capacitive feedback causes the same problems due to the
feedback impedance decrease at higher frequencies). At
higher gains the amplifier is more stable, so RF can be
decreased in a trade-off of stability for bandwidth. The table
below lists recommended RF values for various gains, and the
expected bandwidth.
ACL
RF (Ω)
BW (MHz)
+1
510
850
-1
430
580
+2
360
670
+5
150
520
+10
180
240
+19
270
125
Clamp Operation
General
The HFA1130 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the VH and VL terminals (pins 8 and
5) of the amplifier. VH sets the upper output limit, while VL
sets the lower clamp level. If the amplifier tries to drive the
output above VH, or below VL, the clamp circuitry limits the
output voltage at VH or VL (± the clamp accuracy),
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 1 shows a simplified schematic of the HFA1130 input
stage, and the high clamp (VH) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
between the positive and negative inputs. This buffer forces -IN
to track +IN, and sets up a slewing current of (V-IN - VOUT)/RF.
This current is mirrored onto the high impedance node (Z) by
QX3-QX4, where it is converted to a voltage and fed to the output
via another unity gain buffer. If no clamping is utilized, the high
impedance node may swing within the limits defined by QP4 and
QN4. Note that when the output reaches it’s quiescent value, the
current flowing through -IN is reduced to only that small current
(-IBIAS) required to keep the output at the final voltage.
V+
QP3
QP4
50K
QN2
(30K R1
+IN
QP1
ICLAMP
Z
V-
FOR VL)
+1
V+
QN1
QP2
QN5
QN6
QP6
VH
200Ω
QN3
QN4 QP5
V-
-IN
RF
(EXTERNAL)
VOUT
FIGURE 1. HFA1130 SIMPLIFIED VH CLAMP CIRCUITRY
Tracing the path from VH to Z illustrates the effect of the
clamp voltage on the high impedance node. VH decreases
by 2VBE (QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
4
FN3369.4
July 15, 2005
Share Link: 